多输出定时香农电路

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI:10.1109/ISVLSI.2002.1016873

M. Thornton, R. Drechsler, D. M. Miller

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引用次数: 3

摘要

定时香农电路已被提出作为一种综合方法的低功耗优化技术在逻辑水平上，因为整体电路开关概率可以降低。提出了该原理在多输出电路中的改进应用。还包括以面积交换功率减少的技术和最小化总体电路开关概率的方法。给出了这些技术的实验结果并进行了分析。

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Multi-output timed Shannon circuits

Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be reduced. An improvement in the application of this principle for multi-output circuits is presented. Techniques that trade area for power reduction and a method for minimizing the overall circuit switching probability are also included. Experimental results are given and analyzed for these techniques.

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Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002

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