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Proceedings of the 2015 International Conference on Microelectronic Test Structures最新文献

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Silicon measurements of characteristics for passgate/pull-down/pull-up MOSs and search MOS in a 28 nm HKMG TCAM bitcell 在28nm HKMG TCAM位单元中通闸/下拉/上拉MOS和搜索MOS特性的硅测量
Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106140
K. Nii, Kenji Yamaguchi, M. Yabuuchi, N. Watanabe, T. Hasegawa, Shoji Yoshida, T. Okagaki, M. Yokota, K. Onozawa
{"title":"Silicon measurements of characteristics for passgate/pull-down/pull-up MOSs and search MOS in a 28 nm HKMG TCAM bitcell","authors":"K. Nii, Kenji Yamaguchi, M. Yabuuchi, N. Watanabe, T. Hasegawa, Shoji Yoshida, T. Okagaki, M. Yokota, K. Onozawa","doi":"10.1109/ICMTS.2015.7106140","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106140","url":null,"abstract":"Test structures for measuring characteristics of MOS components in 28 nm high-k metal-gate (HKMG) Ternary Content-Addressable memory (TCAM) bitcell are implemented. Proposed TCAM bitcell are including pull-down (PD) and pass-gate (PG) NMOSs, pull-up (PU) PMOSs and search NMOSs, which are built up based on standard 6T SRAM bitcell. It can achieve the small area but symmetrical layout could not be implemented. Each MOS characteristic is measured by test structure and observed over 20 mV Vt offset for each PD and PG NMOS pairs due to asymmetrical layout, whereas there is no difference in PU-PMOS pair. From measurement results we estimate the bit error rates on the supply voltage for TCAM array and predict that the TCAM Vmin for read-operation becomes worse by 42 mV at 5.3-sigma condition compared to that of standard SRAM array. Based on measured bitcell characteristics we designed and fabricated 80-Mbit TCAM test chips with appropriate redundancies, achieving below 740 mV Vmin at 250 MHz operation at 25°C and 85°C.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126537973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Employing an on-die test chip for maximizing parametric yields of 28nm parts 采用片上测试芯片，最大限度地提高28nm零件的参数良率
Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106107
J. Mueller, S. Jallepalli, R. Mooraka, S. Hector
{"title":"Employing an on-die test chip for maximizing parametric yields of 28nm parts","authors":"J. Mueller, S. Jallepalli, R. Mooraka, S. Hector","doi":"10.1109/ICMTS.2015.7106107","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106107","url":null,"abstract":"We show that a well designed suite of process observation structures (POSt) that can be tested on a standard production tester is a valuable asset for achieving high parametric yields. Our ability to tailor test coverage and conditions based on circuit yield signatures has allowed us to obtain the needed learning within a small test time budget.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130480608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A fully-automated methodology and system for printed electronics foil characterization 用于印刷电子箔表征的全自动方法和系统
Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106138
F. Vila, J. Pallares, Adrià Conde, L. Terés
{"title":"A fully-automated methodology and system for printed electronics foil characterization","authors":"F. Vila, J. Pallares, Adrià Conde, L. Terés","doi":"10.1109/ICMTS.2015.7106138","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106138","url":null,"abstract":"This paper presents a new characterization setup for Printed Electronics. The proposed system allows automatic generation of experiments, optical and electrical characterization, and statistical result analysis of full printed foils. Although its primary objective is the extraction of the needed post-layout corrections, due to its modular design, it can extract other technology information, like Design Rule values or overall printing quality of the whole fabrication process.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133073470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Measurement and modeling of IC self-heating including cooling system properties 集成电路自热包括冷却系统性能的测量和建模
Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106115
T. Nishimura, H. Tanoue, Y. Oodate, H. Mattausch, M. Miura-Mattausch
{"title":"Measurement and modeling of IC self-heating including cooling system properties","authors":"T. Nishimura, H. Tanoue, Y. Oodate, H. Mattausch, M. Miura-Mattausch","doi":"10.1109/ICMTS.2015.7106115","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106115","url":null,"abstract":"Heating and cooling mechanisms under actual IC-operating conditions are investigated experimentally and theoretically. For the investigation different chip packages and cooling-system approaches are studied. Comparison between experimental and theoretical studies concludes that the optimum possible package design is obtained by enhancing both the heat radiation and the air convection at the same time.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125032809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization of wideband decoupling power line with extremely low characteristic impedance for millimeter-wave CMOS circuits 毫米波CMOS电路超低特性阻抗宽带去耦电力线的特性研究
Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106098
R. Goda, S. Amakawa, K. Katayama, K. Takano, T. Yoshida, M. Fujishima
{"title":"Characterization of wideband decoupling power line with extremely low characteristic impedance for millimeter-wave CMOS circuits","authors":"R. Goda, S. Amakawa, K. Katayama, K. Takano, T. Yoshida, M. Fujishima","doi":"10.1109/ICMTS.2015.7106098","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106098","url":null,"abstract":"A wideband decoupling power line for millimeter-wave circuits can be realized with a transmission line having an extremely low characteristic impedance, Z0 → 0Ω. It is, however, very difficult to characterize such a line with the ordinary two-port S-parameter measurement. This paper presents an alternative measurement technique that uses transmission line stubs. The measurement results confirm that a power line impedance below 1Ω is successfully achieved over a very wide frequency range (> 80 GHz). A measurement-based method of finding the necessary length of such a low-impedance line for realizing good decoupling is also proposed.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122073833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Circuit architecture and measurement technique to reduce the leakage current stemming from peripheral circuits with an array structure in examining the resistive element 在检测阻性元件时，采用阵列结构降低外围电路泄漏电流的电路结构和测量技术
Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106096
Shingo Sato, Takaki Ito, Y. Omura
{"title":"Circuit architecture and measurement technique to reduce the leakage current stemming from peripheral circuits with an array structure in examining the resistive element","authors":"Shingo Sato, Takaki Ito, Y. Omura","doi":"10.1109/ICMTS.2015.7106096","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106096","url":null,"abstract":"A circuit architecture and measurement technique are proposed to reduce the leakage current that passes through peripheral circuits when examining arrays of resistive elements. We reveal, with the aid of circuit simulations, that high resolution measurements of resistive elements can be realized with the stacked column-selection array and the addition of a leakage-control terminal.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127982557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel new gate charge measurement method 一种新的栅极电荷测量方法
Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106124
A. Mikata, H. Kakitani, R. Takeda, Alan Wadsworth
{"title":"A novel new gate charge measurement method","authors":"A. Mikata, H. Kakitani, R. Takeda, Alan Wadsworth","doi":"10.1109/ICMTS.2015.7106124","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106124","url":null,"abstract":"The drive for ever-increasing power circuit efficiencies ensures that the measurement of gate charge (Qg) will continue to grow in importance. In this paper, we explain a new Qg measurement method that solves many conventional Qg measurement issues. The outlined method supplies the same Qg curve obtained by traditional one-pass high-power measurement techniques using a new method that combines two Qg curves measured under lower power conditions.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130452512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization of recessed Ohmic contacts to AlGaN/GaN AlGaN/GaN凹槽欧姆接触的表征
Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106133
M. Hajłasz, J. Donkers, S. Sque, S. Heil, D. Gravesteijn, F. Rietveld, J. Schmitz
{"title":"Characterization of recessed Ohmic contacts to AlGaN/GaN","authors":"M. Hajłasz, J. Donkers, S. Sque, S. Heil, D. Gravesteijn, F. Rietveld, J. Schmitz","doi":"10.1109/ICMTS.2015.7106133","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106133","url":null,"abstract":"In this work the choice of appropriate test structures and characterization methods for recessed Ohmic contacts to AlGaN/GaN is discussed. It is shown that, in the worst-case scenario, the prevailing assumption of identical sheet resistance between and under the contacts can lead to errors of up to 3000 % in the extracted specific contact resistance.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131638531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
SPICE modeling of 55 nm embedded SuperFlash® technology 2T memory cells 55纳米嵌入式SuperFlash®技术2T存储单元的SPICE建模
Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106102
S. Martinie, O. Rozeau, M. Tadayoni, C. Raynaud, E. Nowak, S. Hariharan, N. Do
{"title":"SPICE modeling of 55 nm embedded SuperFlash® technology 2T memory cells","authors":"S. Martinie, O. Rozeau, M. Tadayoni, C. Raynaud, E. Nowak, S. Hariharan, N. Do","doi":"10.1109/ICMTS.2015.7106102","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106102","url":null,"abstract":"Embedded Flash NVM has become a key component in many applications, such as data processing, industrial electronics, automotive electronics, consumer electronics and wireless communications. SuperFlash® technology is based on the split-gate concept, using source-side electron injection for programming. The aim of this work is to propose, for the first time, a SPICE macro-model of the 2T (Select Gate and Floating Gate) 3rd generation SuperFlash cell [Hidaka], implemented in a 55 nm CMOS technology. A parameter extraction procedure is also proposed, showing a good agreement between the model and measurements.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134129430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A test structure for reliability analysis of CMOS devices under DC and high frequency AC stress 一种用于分析CMOS器件在直流和高频交流应力下可靠性的测试结构
Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106114
T. Matsuda, K. Ichihashi, H. Iwata, T. Ohzone
{"title":"A test structure for reliability analysis of CMOS devices under DC and high frequency AC stress","authors":"T. Matsuda, K. Ichihashi, H. Iwata, T. Ohzone","doi":"10.1109/ICMTS.2015.7106114","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106114","url":null,"abstract":"A test structure for reliability analysis of MOSFETs in CMOS inverters under DC and high frequency AC stress has been presented. It has an input pulse generation block with a ring oscillator, monitor inverter blocks and Kelvin connected selector switches. Detailed I - V characteristics of MOSFETs in the monitor inverters were measured and the degradation by HCI and BTI in nMOS and pMOS devices were analyzed. The dominant degradation origins in nMOS and pMOS devices can be attributed to HCI and NBTI, respectively.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130092998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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