Proceedings of the 2015 International Conference on Microelectronic Test Structures最新文献

Compact modeling solution of layout dependent effect for FinFET technology FinFET技术布局依赖效应的紧凑建模解决方案

Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106119

David Chen, G. Lin, Tien Hua Lee, Ryan Lee, Y. C. Liu, Meng Fan Wang, Yi Ching Cheng, D. Y. Wu

引用次数: 11

Cross-correlation of electrical measurements via physics-based device simulations: Linking electrical and structural characteristics 通过基于物理的设备模拟的电气测量的相互关联:连接电气和结构特性

Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106117

A. Padovani, L. Larcher, L. Vandelli, M. Bertocchi, R. Cavicchioli, D. Veksler, G. Bersuker

{"title":"Cross-correlation of electrical measurements via physics-based device simulations: Linking electrical and structural characteristics","authors":"A. Padovani, L. Larcher, L. Vandelli, M. Bertocchi, R. Cavicchioli, D. Veksler, G. Bersuker","doi":"10.1109/ICMTS.2015.7106117","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106117","url":null,"abstract":"We present a comprehensive simulation framework to interpret electrical characteristics (I-V, C-V, G-V, Charge-Pumping, BTI, CVS, RVS, ...) commonly used for material characterization and reliability analysis of gate dielectric stacks in modern semiconductor devices. By accounting for the physical processes controlling charge transport through the dielectric (e.g. carrier trapping/de-trapping at the defect sites, defect generation, etc.), which is modeled using a novel approach based of material characteristics [1], [2], the simulations provide a unique link between the electrical measurements data and specific atomic defects in the dielectric stack. Within this methodology, the software allows an accurate defect spectroscopy by cross-correlating measurements of pre-stress electrical parameters (IV, CV, BTI). These data are then used to project the stack reliability through the simulations of stress-induced leakage current (SILC) and time-dependent dielectric degradation trends, demonstrating the tool capabilities as a technology characterization/optimization benchmark.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133538299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Accelerating 14nm device learning and yield ramp using parallel test structures as part of a new inline parametric test strategy 利用并行测试结构加速14nm器件学习和良率斜坡，作为新的在线参数测试策略的一部分

Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106106

Garry Moore, J. Liao, Scott McDade, B. Verzi

引用次数: 8

Electromagnetic field test structure chip for back end of the line metrology 用于后端线路计量的电磁场测试结构芯片

Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106101

Lin You, J. Ahn, Emily Hitz, J. Michelson, Y. Obeng, J. Kopanski

{"title":"Electromagnetic field test structure chip for back end of the line metrology","authors":"Lin You, J. Ahn, Emily Hitz, J. Michelson, Y. Obeng, J. Kopanski","doi":"10.1109/ICMTS.2015.7106101","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106101","url":null,"abstract":"A test chip to produce known and controllable gradients of surface potential and magnetic field at the chip surface and suitable for imaging with various types of scanning probe microscopes is presented. The purpose of the test chip is to evaluate various SPMs as metrology tools to image electro-magnetic fields within nanoelectronic devices and multi-level interconnects, and as metrology tools to detect defects in back end of line (BEOL) metallization and packaging processes. Four different levels of metal are used to create different buried structures that, when biased, will produce varying electric field and magnetic field distributions. Contacts to the chip are made via wire bonds to a printed circuit board (PCB) that allows programed external biases and ground to be applied to specific metal levels while imaging with a SPM. DC and high frequency COMSOL simulations of the test structures were conducted to determine the expected field distributions. Electric field can be imaged via scanning Kelvin force microscopy (SKFM); magnetic field via scanning magnetic force microscopy (MFM); and the capacitance of buried metal lines via scanning microwave microscopy (SMM). The combination of precisely known structures and accurate simulations will allow the spatial resolution and accuracy of various SPMs sensitive to electric field (potential) or magnetic field to be determined and improved.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122282668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Test structures for the wafer mapping and correlation of electrical, mechanical and high frequency magnetic properties of electroplated ferromagnetic alloy films 电镀铁磁合金薄膜电学、力学和高频磁性能的晶圆映射和相关性测试结构

Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106137

E. Sirotkin, S. Smith, R. Walker, J. Terry, A. Walton

引用次数: 3

Compact modeling and parameter extraction strategy of normally-on MOSFET 正常导通MOSFET的紧凑建模及参数提取策略

Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106103

T. Umeda, Y. Hirano, D. Suzuki, A. Tone, T. Inoue, H. Kikuchihara, M. Miura-Mattausch, H. Mattausch

引用次数: 0

Elastic instabilities induced large surface strain sensing structures (EILS) 大表面应变传感结构(EILS)的弹性不稳定性

Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106116

Y. Li, J. Terry, S. Smith, A. Walton, G. McHale, B. Xu

引用次数: 1

14nm BEOL TDDB reliability testing and defect analysis 14nm BEOL TDDB可靠性测试及缺陷分析

Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106094

T. Kane

{"title":"14nm BEOL TDDB reliability testing and defect analysis","authors":"T. Kane","doi":"10.1109/ICMTS.2015.7106094","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106094","url":null,"abstract":"14nm BEOL (back end of line) TDDB (time to dielectric defect breakdown) test site structures successfully detect reliability defects but pose significant challenges in defect analysis At these advanced technology nodes, the reduction in copper land cross sectional area is accompanied by increased current density and electromigration failure rates. TDDB reliability test structures must be sensitive to capturing reliability defects. These same TDDB test site structures combined with porous ultra low-k (ULK) dielectric films represent real challenges in localizing and then determining BEOL reliability defects. Defect localization is difficult due to the complexity of these multiple metal layers along with the presence of the porous, low k dielectric films which exhibit shrinkage or void formation when exposed to an e-beam/FIB ion beam > 1 keV. Due to the porosity of these ULK dielectric films, they are especially susceptible to gallium ion implantation. It has been reported elsewhere that suppressing copper diffusion at the copper land/cap interface can be achieved by depositing a thin layer of CoWP and doping the copper seed layer with manganese [15, 16, 17]. However, a method for analytically confirming that these approaches for suppressing the copper diffusion do not affect TDDB performance/electromigration behavior must be demonstrated.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121999698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

NPN CML ring oscillators for model verification and process monitoring 用于模型验证和过程监控的NPN CML环形振荡器

Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106118

Cory Compton

引用次数: 1

Measurement of Vth variation due to STI stress and inverse narrow channel effect at ultra-low voltage in a variability-suppressed process 在变异性抑制过程中测量超低电压下由STI应力和反向窄通道效应引起的Vth变化

Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI: 10.1109/ICMTS.2015.7106122

Y. Ogasahara, M. Hioki, T. Nakagawa, T. Sekigawa, T. Tsutsumi, H. Koike

引用次数: 1