正常导通MOSFET的紧凑建模及参数提取策略

Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI:10.1109/ICMTS.2015.7106103

T. Umeda, Y. Hirano, D. Suzuki, A. Tone, T. Inoue, H. Kikuchihara, M. Miura-Mattausch, H. Mattausch

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引用次数: 0

摘要

正常导通mosfet的额外沟道掺杂层导致沟道表面附近的积累层电流和p/n结上方更深的中性区电流，它们分别主导平带上下的偏置条件。所开发的紧凑模型可以准确地捕获这些电流，并利用它们不同的偏置条件特性进行有效的参数提取。

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Compact modeling and parameter extraction strategy of normally-on MOSFET

The additional channel-dopant layer of normally-on MOSFETs leads to accumulation-layer current near channel surface and deeper-lying neutral-region current above the p/n junction, which dominate bias conditions above and below flat-band, respectively. The developed compact model accurately captures these currents and exploits their different bias-condition properties for efficient parameter extraction.

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Proceedings of the 2015 International Conference on Microelectronic Test Structures

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