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2020 International Symposium on Devices, Circuits and Systems (ISDCS)最新文献

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History Effect on Circuit Performance of SOI-MOSFETs 历史对soi - mosfet电路性能的影响
2020 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2020-03-04 DOI: 10.1109/ISDCS49393.2020.9262980
Soumajit Ghosh, M. Miura-Mattausch, T. Iizuka, H. Kikuchihara, H. Rahaman, H. Mattausch
{"title":"History Effect on Circuit Performance of SOI-MOSFETs","authors":"Soumajit Ghosh, M. Miura-Mattausch, T. Iizuka, H. Kikuchihara, H. Rahaman, H. Mattausch","doi":"10.1109/ISDCS49393.2020.9262980","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262980","url":null,"abstract":"The history effect observed in SOI-MOSFET is investigated. Origin of the effect is the impact ionization, where induced carriers are accumulated within the SOI layer due the potential barrier at the source/channel junction. The compact model HiSIM_SOTB describing the effect based on its origin is studied to analyze the influence on circuit. An inverter-chain circuit is applied to characterize the influence of the history effect. It is demonstrated how the accumulated carriers propagates within the circuit as well as how the generated carriers are accumulated and disappeared during circuit operation. The charging/discharging of the carriers takes time until it reaches stable condition, which could be much longer than the normal circuit operation cycle, observed as the history effect.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129495873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Force-Sensor-Based Walking-Environment Recognition of Biped Robots 基于力传感器的双足机器人行走环境识别
2020 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2020-03-04 DOI: 10.1109/ISDCS49393.2020.9263005
H. Mattausch, A. Luo, S. Dutta, T. Maiti, M. Miura-Mattausch
{"title":"Force-Sensor-Based Walking-Environment Recognition of Biped Robots","authors":"H. Mattausch, A. Luo, S. Dutta, T. Maiti, M. Miura-Mattausch","doi":"10.1109/ISDCS49393.2020.9263005","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263005","url":null,"abstract":"Usability of biped robots in real applications depends on the robot capability of stable and robust walking with high efficiency. To cope with the various practical challenges, the robot must therefore be able to recognize its environment properties. We report a system for indoor-surface detection based on force sensors attached below the feet of the robot. To verify the recognition performance, indoor evaluation surfaces with 5 different properties are used. The capability of fast surface-property recognition is realized by processing the stream of force-sensor data according to the method of overlapping sliding windows, in order to generate 4 different features in a dynamic way. A k-nearest-neighbor (kNN) classifier with multiple classes is applied for real-time high- accuracy recognition of the surface-specific robot-walking characteristics. In particular, recognition performance can be increased by combining the studied features into a single feature descriptor, instead of using each feature separately. Achievability of an overall accuracy of 90.4% and an average precision of 91.49% is verified. Thus, a favorable trade-off between cost and performance is realized. The developed method is useful for optimized dynamic robot-body balancing and walking-speed adjustment, according to the recognized surface properties.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128245493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Heat Mitigation in 3D ICs by Improvised TTSV Structure 基于简易TTSV结构的3D集成电路散热研究
2020 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2020-03-04 DOI: 10.1109/ISDCS49393.2020.9262977
Debika Chaudhuri, Dalia Nandi Das, H. Rahaman, Tamal Ghosh
{"title":"Heat Mitigation in 3D ICs by Improvised TTSV Structure","authors":"Debika Chaudhuri, Dalia Nandi Das, H. Rahaman, Tamal Ghosh","doi":"10.1109/ISDCS49393.2020.9262977","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262977","url":null,"abstract":"To get rid of the diverse factors and limitations originated in the conventional planer integration design, 3-dimensional (3D) integration seems to be one of the best replacing signatures in current era. But, thermal issues are the major constraint for the wide spread application, further growth and advancement to these highly budding integration techniques. To reduce the generated heat within the 3D IC cooling through the thermal through silicon via (TTSV) is one of the best possible recognized techniques. This paper is intended to provide some realistic regulation to the design of TTSV for effective management thermal heat mitigation. The temperature dependent results for the hotspot alignment issues are also discussed and compared for different TTSV outer materials along with the utilization of time dependent temperature fluctuation generated within the 3D IC active layers.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124334480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Investigation of density and alignment of ZnO-nanowires grown by double-step chemical bath deposition (CBD/CBD) technique on metallic, insulating and semiconducting substrates 双步化学浴沉积(CBD/CBD)技术在金属、绝缘和半导体基底上生长zno纳米线的密度和取向研究
2020 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2020-03-04 DOI: 10.1109/ISDCS49393.2020.9262979
S. Bhattacharya, R. Saha, Subhrajit Sikdar, S. Mandal, Chirantan Das, S. Chattopadhyay
{"title":"Investigation of density and alignment of ZnO-nanowires grown by double-step chemical bath deposition (CBD/CBD) technique on metallic, insulating and semiconducting substrates","authors":"S. Bhattacharya, R. Saha, Subhrajit Sikdar, S. Mandal, Chirantan Das, S. Chattopadhyay","doi":"10.1109/ISDCS49393.2020.9262979","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262979","url":null,"abstract":"In this paper, the impact of various metallic, insulating and semiconducting substrates on the growth of ZnO nanowires is investigated. The nanowire density and its alignment are studied for all of the substrates and it is observed that the substrate with relatively lower lattice mismatch shows higher degree of nanowire density and alignment. The formation of such nanowires is confirmed by performing EDS, XRD and UV-Vis spectrophotometry experiments. The current work may be useful for mass production of highly ordered ZnO-nanowires for numerous applications.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122498682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation of HfSiOX Passivation Effect on AlGaN/GaN HEMT HfSiOX对AlGaN/GaN HEMT钝化效果的研究
2020 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2020-03-04 DOI: 10.1109/ISDCS49393.2020.9262998
S. Mazumder, Yeong-Her Wang
{"title":"Investigation of HfSiOX Passivation Effect on AlGaN/GaN HEMT","authors":"S. Mazumder, Yeong-Her Wang","doi":"10.1109/ISDCS49393.2020.9262998","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262998","url":null,"abstract":"AlGaN/GaN-based high electron mobility Transistors (HEMTs) were fabricated on Si substrate. Surface passivation effect on AlGaN/GaN HEMTs was investigated with hafnium silicate (HfSiOx) passivation layer deposited by atomic layer deposition (ALD) at 250 °C. The DC current-voltage characteristics (ID-VD), pulsed ID-VD characteristics, and transfer characteristics of the device were compared before and after passivation. The enhancement of IDMAX and GMMAX with better gate controllability as well as significant reduction of current degradation phenomenon due to the suppression of surface states, was observed in the passivated (HfSiOX) HEMT compared to unpassivated device","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126272473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Image Classification Based on Approximate Wavelet Transform and Transfer Learning on Deep Convolutional Neural Networks 基于近似小波变换和深度卷积神经网络迁移学习的图像分类
2020 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2020-03-04 DOI: 10.1109/ISDCS49393.2020.9263001
Moumita Acharya, Soumyajit Poddar, A. Chakrabarti, H. Rahaman
{"title":"Image Classification Based on Approximate Wavelet Transform and Transfer Learning on Deep Convolutional Neural Networks","authors":"Moumita Acharya, Soumyajit Poddar, A. Chakrabarti, H. Rahaman","doi":"10.1109/ISDCS49393.2020.9263001","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263001","url":null,"abstract":"In this paper a novel method has been proposed based on a combination of approximate computing, Discrete Wavelet Transform and deep neural network for image classification. In the recent trends, image classification using deep learning network comes under the limelight of the world of artificial intelligence. In the paper we have applied the approximation through bit width reduction technique through discrete wavelet transform technique for the processing of the input database. For feature extraction and classification we have developed a deep convolution neural network that is trained with that preprocesses data. The results show that the proposed model reduces the elapsed time and achieve a good rate of accuracy as compare to the Alexnet and Resnet-50 CNN models.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116675505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Microfluidic Cyberphysical Diagnostic System: An ANN Based Application 微流控网络物理诊断系统:基于神经网络的应用
2020 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2020-03-04 DOI: 10.1109/ISDCS49393.2020.9263010
P. Roy, Amiya Sahoo, Mriganka Chakrabarty, H. Rahaman
{"title":"Microfluidic Cyberphysical Diagnostic System: An ANN Based Application","authors":"P. Roy, Amiya Sahoo, Mriganka Chakrabarty, H. Rahaman","doi":"10.1109/ISDCS49393.2020.9263010","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263010","url":null,"abstract":"The present day advances in Microfluidic and Microfabrication technology resulted in the emergence of a new generation of lab-on-chip (LOC) devices namely digital microfluidic biochips. Such devices find wide application in the area of medical diagnostics, forensics, sequencing of DNA, design of drugs, monitoring of environment and so on. Automated optical detection and analysis plays significant role in interpretation and decision making in medical diagnostics using lab-on-chip based applications. This paper proposes a cyber physical system based on artificial neural networks to perform a sequential multilevel detection for enhanced medical detection and diagnostics for accurate treatment procedure. The Biochip based detection and diagnosis is simulated in an FPGA platform. The simulation results are found to be closely accurate with conventional techniques and highly encouraging.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134474067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Improved Online Testing Technique For Reversible Circuits 一种改进的可逆电路在线测试技术
2020 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2020-03-04 DOI: 10.1109/ISDCS49393.2020.9262971
Joyati Mondal, D. K. Das
{"title":"An Improved Online Testing Technique For Reversible Circuits","authors":"Joyati Mondal, D. K. Das","doi":"10.1109/ISDCS49393.2020.9262971","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262971","url":null,"abstract":"The emerging technology of reversible circuits offers a potential solution to the synthesis of ultra low-power quantum computing systems. A reversible circuit can be envisaged as a cascade of reversible gates only, such as Toffoli gate, which has two components: k control bits and a target bit (k-CNOT), k ≥1. While analyzing testability issues in a reversible circuit, the missing-gate fault model is often used for modeling physical defects in k-CNOT gates. In this paper, we propose online design-for-testability (DFT) technique. The proposed method is an improved version of an earlier work by Kole et. al. Our method yields less overhead in terms of quantum cost as compared to the original approach. The method is advantageous for circuits where consecutive gates occur frequently with the same set of controls.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123605586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Classification of ECG Signals for IoT-based Smart Healthcare Applications using WBAN 基于物联网的WBAN智能医疗应用的心电信号分类
2020 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2020-03-04 DOI: 10.1109/ISDCS49393.2020.9263011
Arka Roy, S. Chatterjee, Prasenjit Maji, H. Mondal
{"title":"Classification of ECG Signals for IoT-based Smart Healthcare Applications using WBAN","authors":"Arka Roy, S. Chatterjee, Prasenjit Maji, H. Mondal","doi":"10.1109/ISDCS49393.2020.9263011","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263011","url":null,"abstract":"From the last few decades, the diagnoses of diseases are based on a medical test. Electrocardiogram (ECG) signal is one of the techniques used for diagnosing heart diseases. The Electrocardiograph or ECG machine allows removing many electrical and mechanical defects of the heart by measuring ECG’s which have some potential on the body surface. With the help of it, doctors are able to determine heart rate and other cardiac parameters. Early and accurate detection of arrhythmia types is important in detecting heart diseases and finding treatment for a patient. This paper deals with the analysis of the signal for the classification of critical and non-critical data using different learning-based algorithms for smart Internet of Things (IoT) based health-care monitoring application using Wireless Body Area Network (WBAN) and how to minimize the misclassified critical data.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121019710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of AlGaN Doping Concentration on the Analog/RF Performance of a Double Gate Underlap n-AlGaN/GaN MOSHEMT AlGaN掺杂浓度对双栅下搭接n-AlGaN/GaN MOSHEMT模拟/射频性能的影响
2020 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2020-03-04 DOI: 10.1109/ISDCS49393.2020.9263012
Rajrup Mitra, Akash Roy, A. Kundu, M. Kar
{"title":"Impact of AlGaN Doping Concentration on the Analog/RF Performance of a Double Gate Underlap n-AlGaN/GaN MOSHEMT","authors":"Rajrup Mitra, Akash Roy, A. Kundu, M. Kar","doi":"10.1109/ISDCS49393.2020.9263012","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263012","url":null,"abstract":"With a well calibrated TCAD Simulator, this paper characterizes a novel n-AlGaN/GaN Metal Oxide Semiconductor High Electron Mobility Transistor (MOSHEMT) with a double gate symmetric underlapped structure. Detailed Analog, Power Gain and RF Parameters have been studied by varying the AlGaN doping concentration from undoped to 5x1018/cm3. These enhanced hetero-structures display superior performance in high frequency and low power applications compared to conventional HEMT and MOSFET devices.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120938207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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