2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)最新文献_第9页

Generation and Tracking of Optical Signals inside the IC to Improve Device Security and Failure Analysis 集成电路内部光信号的产生和跟踪，提高器件安全性和故障分析

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984916

E. Amini, N. Herfurth, A. Beyreuther, Jean-Pierre Seifert, C. Boit

{"title":"Generation and Tracking of Optical Signals inside the IC to Improve Device Security and Failure Analysis","authors":"E. Amini, N. Herfurth, A. Beyreuther, Jean-Pierre Seifert, C. Boit","doi":"10.1109/IPFA47161.2019.8984916","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984916","url":null,"abstract":"Optical signal tracking techniques accessing the IC through the chip backside have become the most successful methods in hardware attacks. On the other hand, tracking the optical signal can be employed to protect the IC against such attacks. Furthermore, this technique is an advantageous method for failure analysis. Tracking the optical signal reflected from, or transmitted through a surface, reveals some information about this surface that can be used to monitor the surface. Thus, detection of the light reflected from the silicon chip back surface discloses any harms and violations to the backside. For this purpose, we need to generate light inside the IC, which is possible by applying forward bias to a p-n junction. However, in most ICs, silicon is the base material, and the light generated by silicon LED is weak. Furthermore, this application may lead to degradation of the silicon LED. Therefore, an externally produced a stronger light source mounted onto the chip is desirable. This paper considers possible ways to generate and track optical signals inside the silicon to achieve a proper protection structure that prevents attacks from being carried out through the silicon back surface. We describe how an efficient LED can be integrated into an IC to illuminate light in the demanded directions, as well as which kind of LED is favorable for this target.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128549592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Study of n-LDMOS Off-state Breakdown Degradation with 0.18μm BCD Technology 基于0.18μm BCD技术的n-LDMOS脱态击穿降解研究

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984858

Feng Lin, Bin Yang, Guipeng Sun, Shuxian Chen, Chunxu Li, Yu Huang, Qiong Wang, Siyang Liu

引用次数: 1

Impact of low temperature on the TSG Vt shift during erase cycling of 3-D NAND Flash memory 低温对3-D NAND闪存擦除循环中TSG Vt位移的影响

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984850

Da Li, Z. Huo, Jianhua Feng, Lei Jin, Liang Yan, Xinlei Jia, Jianquan Jia, Yali Song, An Zhang, Feng Xu, Wei Hou

引用次数: 1

Using Microprobe to enhance Die Level Static Fault Isolation in Complex IC 用微探头提高复杂集成电路的模级静态故障隔离

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984821

D. Nagalingam, A. Quah, S. Moon, S. M. Parab, P. T. Ng, S. L. Ting, H.H. Ma, C.Q. Chen

{"title":"Using Microprobe to enhance Die Level Static Fault Isolation in Complex IC","authors":"D. Nagalingam, A. Quah, S. Moon, S. M. Parab, P. T. Ng, S. L. Ting, H.H. Ma, C.Q. Chen","doi":"10.1109/IPFA47161.2019.8984821","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984821","url":null,"abstract":"Modern SoC design incorporates power management circuits to minimize standby leakages of digital logic circuitry. This isolates the logic blocks from being directly powered by the IC’s pad level power supply and ground. As a result, die level static fault isolation became ineffective even for gross defects that are shorting the power lines in the logic blocks due to gated supply. From the foundry standpoint, fault isolation on such devices are even more challenging without the product knowhow, device specific hardware and test program to properly condition the power management circuits. An alternative method is to bypass the power control circuits through microprobing on the top metal traces to directly supply power to the logic blocks. However, the key challenge to this method is the means to identify these power gated devices and verify the relevant power traces to microprobe, sometimes even in situations without layout information. In this paper, 3 different approaches have been illustrated using 3 case studies to overcome this challenge and achieve static fault isolation success on power gated devices.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128420548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cycle-Shift Scan Chain Failure Analysis Using Single Pulse Test Pattern 用单脉冲测试模式分析周期移位扫描链失效

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984902

Paulraj Eric, C. Choong, Yiang Won Chai

引用次数: 1

Leakage Current Degradation in SiC Junction Barrier Schottky Diodes under Heavy Ion Microbeam 重离子微束作用下SiC结势垒肖特基二极管的泄漏电流退化

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984872

Shu-rui Cao, Qingkui Yu, Guanghua Du, Jinlong Guo, Wang He, Hongwei Zhang, Sun Yi

引用次数: 13

Study of Internal Latchup Behaviors in Advanced Bulk FinFET Technology 先进体FinFET技术内部锁紧特性研究

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984897

Wei Liang, R. Gauthier, S. Mitra, You Li, Chen Yan

引用次数: 4

Defect Density Reduction of Thin SiO2 MOSFET through Oxidation Pre-cleaning improvement – a Fast Wafer Level Reliability Monitoring 通过氧化预清洗改进降低薄SiO2 MOSFET缺陷密度-快速晶圆级可靠性监测

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984760

M. H. Kamaruddin, N. Soin, C. Veriven, C.M. How, C. K. Ang

{"title":"Defect Density Reduction of Thin SiO2 MOSFET through Oxidation Pre-cleaning improvement – a Fast Wafer Level Reliability Monitoring","authors":"M. H. Kamaruddin, N. Soin, C. Veriven, C.M. How, C. K. Ang","doi":"10.1109/IPFA47161.2019.8984760","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984760","url":null,"abstract":"We conducted experiment to reduce the level defect density in 7.5nm thin SiO2 CMOS by improving the pre-cleaning of silicon surface before gate oxidation. Fast wafer level reliability monitoring is implemented using ramped voltage stress (RVS) where from the breakdown Weibull chart, the inclination point of intrinsic and extrinsic will give the measurement of defect density (unit is number of defect per cm2). We measured high defect density of >20 times the defect density target. Through systematic problem solving methodology, root cause was found to be due to ineffective cleaning method. With the additional SPM cleaning in the gate oxidation pre-clean step, defect density reduced by almost 95%. SPM chemistry reduces the surface roughness and also improves contaminations removal on the wafer surface prior to gate oxidation. Rougher interface of Si-SiO2 leads to early failure and lower TDDB. Inline silicon surface roughness check is not practical due to very small nature of embedded-type contaminants a rough silicon surface creates. In order to increase detection probability of micro-sized particles, a good reliability monitoring strategy using special test structures is implemented.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134234612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

In-depth Analysis of 10 nm Exynos Processor using Micro CT and FIB-SEM System 利用Micro CT和FIB-SEM系统对10nm Exynos处理器进行深入分析

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984907

S. Sharang, J. Dluhoš, D. Kalasová, A. Denisyuk, R. Váňa, T. Zikmund, J. Kaiser, J. Oboňa

引用次数: 0

Three-dimensional Structure Recognition of Circuit Patterns on Semiconductor Devices Using Multiple SEM Images Detected in Different Electron Scattering Angles 基于不同电子散射角度的多幅扫描电镜图像的半导体器件电路图形三维结构识别

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984877

K. Yasui, M. Osaki, A. Miyamoto, Hitoshi Namai

{"title":"Three-dimensional Structure Recognition of Circuit Patterns on Semiconductor Devices Using Multiple SEM Images Detected in Different Electron Scattering Angles","authors":"K. Yasui, M. Osaki, A. Miyamoto, Hitoshi Namai","doi":"10.1109/IPFA47161.2019.8984877","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984877","url":null,"abstract":"We propose a method for recognizing the three-dimensional structure of circuit patterns to achieve automatic pattern width measurement of semiconductor devices using scanning electron microscope (SEM). Pattern measurement requires pattern recognition technique to identify the measurement position from an SEM image. However, pattern width and brightness values on an image fluctuate according to patterning conditions, type of material, etc., so distinguishing between line and space through image matching based on brightness information is difficult. In view of this problem, we investigated a line and space discrimination method that focuses on fundamentally different three-dimensional structures (concavity and convexity) and considering that this difference between concavity and convexity appears as a difference in the scattering angles of secondary electrons, we captured two images corresponding to these two scattering angles. In this way, we were able to design image feature that portray the difference between line and space from these two images and perform high-speed and easy capture of concavity and convexity information. In experiments, the proposed method achieved a 100% accuracy rate in automatic critical-dimension measurements.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130937547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2