Using Microprobe to enhance Die Level Static Fault Isolation in Complex IC

Modern SoC design incorporates power management circuits to minimize standby leakages of digital logic circuitry. This isolates the logic blocks from being directly powered by the IC’s pad level power supply and ground. As a result, die level static fault isolation became ineffective even for gross defects that are shorting the power lines in the logic blocks due to gated supply. From the foundry standpoint, fault isolation on such devices are even more challenging without the product knowhow, device specific hardware and test program to properly condition the power management circuits. An alternative method is to bypass the power control circuits through microprobing on the top metal traces to directly supply power to the logic blocks. However, the key challenge to this method is the means to identify these power gated devices and verify the relevant power traces to microprobe, sometimes even in situations without layout information. In this paper, 3 different approaches have been illustrated using 3 case studies to overcome this challenge and achieve static fault isolation success on power gated devices.