2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)最新文献_第3页

Silicon Precipitates Counts and Size Study in Aluminium Bond Pads 铝焊盘中硅析出物的数量和尺寸研究

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984865

L. W. Lee, Mohamad Esa Azlin MohdNoor, M. M. Raj

引用次数: 0

Enhancing the SRAM Failure Analysis Process 加强SRAM失效分析过程

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984841

R. Mendaros

{"title":"Enhancing the SRAM Failure Analysis Process","authors":"R. Mendaros","doi":"10.1109/IPFA47161.2019.8984841","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984841","url":null,"abstract":"The advent of the 65nm silicon fabrication technology node and smaller geometries; particularly for static random-access memory (SRAM) array, posed several Failure Analysis (FA) challenges such as the fault isolation capability limitations, physical FA (PFA) approach identification intricacy, defect node localization complexity and defect to fail mode correlation difficulty. To address these challenges, device defect modeling (DDM) process through software simulations and building of defect databases were introduced. Through the aid of the DDM process, defect sites were reduced to a single transistor or node from the SRAM array. Defect models were derived from the simulation process that guided analysts in identifying the suitable PFA approach. DDM process was effective in the failure mechanism to failure mode simulations. The DDM process was likewise instrumental in building defect databases for SRAM layout designs. These databases contained relevant information such as circuit simulation results, fabrication material stacking, suggested fault isolation techniques and potential defect locations that served as references for analysts.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129213655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Analysis of SEE modes in ferroelectric random access memory using heavy ions 利用重离子分析铁电随机存取存储器中的SEE模式

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984849

Jianan Wei, Hongxia Guo, Fengqi Zhang, G. Guo, Chaohui He

引用次数: 1

The Solutions of Bit Line Failure Analysis: Low kV E-Beam, EBAC and LVI 位线故障分析的解决方法:低千伏电子束、EBAC和LVI

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984867

Link Chang, Rick HC Wang, Andy Chang, Simon T. C. Wang, Yu Pang Chang, C. G. Song

引用次数: 0

Correlation Analysis and Characterization of Micromorphology and Optoelectronic Properties of SiO2/SiC in Pressure Sensor 压力传感器中SiO2/SiC材料微观形貌与光电性能的相关性分析与表征

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984861

Li-mei Rong, Yugang Yin, Jinze He, Jiangfeng Du, T. Luo, Rong‐Ping Yang, Kun Gao, Qi Yu, Jiao Xu, Guang-hong Zhao

引用次数: 0

IPFA 2019 Author Index IPFA 2019作者索引

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/ipfa47161.2019.8984873

引用次数: 0

How To Determine Fluorine Contamination Level On A Normal Al Bondpad? 如何确定正常铝键板上的氟污染水平?

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984826

H. Younan

引用次数: 0

Reliability hazard characterization of wafer-level spatial metrology parameters based on LOF-KNN method 基于LOF-KNN方法的片级空间计量参数可靠性危害表征

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984814

Jinli Zhang, Hailong You, Renxu Jia

引用次数: 2

Enhanced Package Fault Isolation Method Using Time Domain Reflectometry (TDR) Incorporation with Mathematics 时域反射与数学相结合的改进包故障隔离方法

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984800

Lan Yin Lee, Kok Keng Chua

{"title":"Enhanced Package Fault Isolation Method Using Time Domain Reflectometry (TDR) Incorporation with Mathematics","authors":"Lan Yin Lee, Kok Keng Chua","doi":"10.1109/IPFA47161.2019.8984800","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984800","url":null,"abstract":"Time domain reflectometry (TDR) has gained attention in electrical verification for electronic components over the years. TDR works by sending a series of short pulses through a transmission line under investigation, and measures the reflections that result from a signal travelling through a transmission environment. [1], [2] It is often being used for short or open failures defect localization, to isolate whether the short/ open failure is in the die region or package region. With the enhancement of process technology and increase of layers in the package/ silicon die, and due to limitation of reference medium, the results produced by using TDR can only be used as a rough guide, i.e. based on the TDR results, we can only narrow the open/ short failure to be in the die or package, we could not tell which layer of package the short/open is. This paper demonstrates some successful cases with the incorporation of mathematics together with the use of TDR machine. Open failure can be accurately localized down to specific substrate layer via mathematics calculation. Physical failure analysis further confirmed the accuracy of this method by showing the defect at that specific layer in those cases.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125303998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Increased Fault Isolation Efficiency by Using Scan Cell Visualizer for Scan Chain Failures 通过使用扫描单元可视化工具处理扫描链故障，提高了故障隔离效率

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2019-07-01 DOI: 10.1109/IPFA47161.2019.8984846

Peter Chua Thin Wei, Foo Loke Sheng, Ng Kim Choo, K. Serrels, Kuyt Ku, Curt Lin, Tang Chih-yi

{"title":"Increased Fault Isolation Efficiency by Using Scan Cell Visualizer for Scan Chain Failures","authors":"Peter Chua Thin Wei, Foo Loke Sheng, Ng Kim Choo, K. Serrels, Kuyt Ku, Curt Lin, Tang Chih-yi","doi":"10.1109/IPFA47161.2019.8984846","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984846","url":null,"abstract":"Scan design, being part of the most commonly practiced form of Design for Testability (DFT) has been developed to enable software based diagnosis for scan chain failures. Tessent Diagnosis helps to narrow down the reported failures to a suspected failing chain [1] - [5]. Unfortunately, scan chains can consist of hundreds to thousands of individual latches that can represent potential defect candidates and are typically distributed across the entire chip. Implementing global fault isolation techniques, which includes Photon Emission Microscopy (PEM) analysis, can lead to a collection of numerous anomalous emission spots. Cross mapping both the PEM results and the hundreds to thousands of individual scan cells to the CAD layout is both time-consuming and labor intensive. Moreover, selective cross mapping does not reveal the scan latches in chronological order, which is important for any scan chain analysis. One possible solution is to spatially map the scan latch list from the diagnosis file to the CAD layout to visualize the scan latch distribution quickly. This paper describes the use of this Scan Cell Visualizer through the use of case studies to demonstrate improved layout mapping efficiency and reduced overall failure analysis cycle time.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"52 47","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114005911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2