Enhancing the SRAM Failure Analysis Process

Abstract

The advent of the 65nm silicon fabrication technology node and smaller geometries; particularly for static random-access memory (SRAM) array, posed several Failure Analysis (FA) challenges such as the fault isolation capability limitations, physical FA (PFA) approach identification intricacy, defect node localization complexity and defect to fail mode correlation difficulty. To address these challenges, device defect modeling (DDM) process through software simulations and building of defect databases were introduced. Through the aid of the DDM process, defect sites were reduced to a single transistor or node from the SRAM array. Defect models were derived from the simulation process that guided analysts in identifying the suitable PFA approach. DDM process was effective in the failure mechanism to failure mode simulations. The DDM process was likewise instrumental in building defect databases for SRAM layout designs. These databases contained relevant information such as circuit simulation results, fabrication material stacking, suggested fault isolation techniques and potential defect locations that served as references for analysts.