2012 IEEE 30th VLSI Test Symposium (VTS)最新文献_第5页

Comprehensive online defect diagnosis in on-chip networks 片上网络综合在线缺陷诊断

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231078

A. Ghofrani, Ritesh Parikh, S. Shamshiri, A. DeOrio, K. Cheng, V. Bertacco

引用次数: 54

Test algorithms for ECC-based memory repair in nanotechnologies 纳米技术中基于ecc的记忆修复测试算法

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231058

P. Papavramidou, M. Nicolaidis

引用次数: 10

Tester-based optical and electrical diagnostic system and techniques 基于测试仪的光电诊断系统和技术

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231104

P. Song, F. Stellari

引用次数: 2

A SMT-based diagnostic test generation method for combinational circuits 基于smt的组合电路诊断测试生成方法

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231105

S. Prabhu, M. Hsiao, L. Lingappan, V. Gangaram

引用次数: 21

Derating based hardware optimizations in soft error tolerant designs 软容错设计中基于降额的硬件优化

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231067

V. Prasanth, Virendra Singh, R. Parekhji

{"title":"Derating based hardware optimizations in soft error tolerant designs","authors":"V. Prasanth, Virendra Singh, R. Parekhji","doi":"10.1109/VTS.2012.6231067","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231067","url":null,"abstract":"Ensuring reliable operation over an extended period of time is one of the biggest challenges facing present day electronic systems. The increased vulnerability of the components to atmospheric particle strikes poses a big threat in attaining the reliability required for various mission critical applications. Various soft error mitigation methodologies exist to address this reliability challenge. A general solution to this problem is to arrive at a soft error mitigation methodology with an acceptable implementation overhead and error tolerance level. This implementation overhead can then be reduced by taking advantage of various derating effects like logical derating, electrical derating and timing window derating, and/or making use of application redundancy, e.g. redundancy in firmware/software executing on the so designed robust hardware. In this paper, we analyze the impact of various derating factors and show how they can be profitably employed to reduce the hardware overhead to implement a given level of soft error robustness. This analysis is performed on a set of benchmark circuits using the delayed capture methodology. Experimental results show up to 23% reduction in the hardware overhead when considering individual and combined derating factors.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114097944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

On the parametric failures of SRAM in a 3D-die stack considering tier-to-tier supply cross-talk 考虑层间电源串扰的3d芯片堆叠中SRAM的参数失效

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231064

W. Yueh, S. Chatterjee, A. Trivedi, S. Mukhopadhyay

引用次数: 3

Built-in-Self Test of transmitter I/Q mismatch using self-mixing envelope detector 内置自检发射机I/Q不匹配使用自混合包络检测器

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231080

A. Nassery, Srinath Byregowda, S. Ozev, M. Verhelst, M. Slamani

引用次数: 8

A Built-In Self-Test scheme for DDR memory output timing test and measurement DDR内存输出时序测试与测量的内置自检方案

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231072

H. Kim, J. Abraham

{"title":"A Built-In Self-Test scheme for DDR memory output timing test and measurement","authors":"H. Kim, J. Abraham","doi":"10.1109/VTS.2012.6231072","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231072","url":null,"abstract":"This paper presents a Built-In Self-Test (BIST) scheme to measure high speed double data rate (DDR) memory output timing using low cost testers. This technique uses an on-chip pattern generator to generate a time delay between data and data-strobe or clock. The time delay is controlled precisely using a phase interpolator based cycle-by-cycle control method. A novel method for testing the resolution of phase interpolator, which does not need any extra hardware, is also presented. Using the test resolution, a timing pass/fail flag is set and the timing margin is quantified as a multiple of the test clock cycle. Since these test results have high observability, output per-pin timing performance can be diagnosed easily, which is especially good for testing parallel memory interfaces. Moreover, these features make our scheme compatible with low-cost testers and decreases the time-to-market for the chip. The BIST circuit has been implemented using the 0.18-μm CMOS process, and chip measurement results are presented. We obtained a test resolution of 10 ps for testing output timing. Using the fabricated test chip, this paper shows the effects of switching noise, per-pin skews and slew-rate change on output timing variations.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128119816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A Bayesian-based process parameter estimation using IDDQ current signature 基于贝叶斯的IDDQ电流签名过程参数估计

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-01 DOI: 10.1109/VTS.2012.6231085

Michihiro Shintani, Takashi Sato

引用次数: 7

Tutorial 1 教程1

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 1900-01-01 DOI: 10.1109/ats.2006.260981

R. Karri, Peilin Song, O. Sinanoglu

引用次数: 0