2012 IEEE 30th VLSI Test Symposium (VTS)最新文献_第4页

A Memory Failure Pattern Analyzer for memory diagnosis and repair 用于记忆诊断和修复的记忆故障模式分析器

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231059

Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu

引用次数: 9

A pseudo-dynamic comparator for error detection in fault tolerant architectures 容错体系结构中用于错误检测的伪动态比较器

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231079

D. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, M. Imhof, H. Wunderlich

{"title":"A pseudo-dynamic comparator for error detection in fault tolerant architectures","authors":"D. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, M. Imhof, H. Wunderlich","doi":"10.1109/VTS.2012.6231079","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231079","url":null,"abstract":"Although CMOS technology scaling offers many advantages, it suffers from robustness problem caused by hard, soft and timing errors. The robustness of future CMOS technology nodes must be improved and the use of fault tolerant architectures is probably the most viable solution. In this context, Duplication/Comparison scheme is widely used for error detection. Traditionally, this scheme uses a static comparator structure that detects hard error. However, it is not effective for soft and timing errors detection due to the possible masking of glitches by the comparator itself. To solve this problem, we propose a pseudo-dynamic comparator architecture that combines a dynamic CMOS transition detector and a static comparator. Experimental results show that the proposed comparator detects not only hard errors but also small glitches related to soft and timing errors. Moreover, its dynamic characteristics allow reducing the power consumption while keeping an equivalent silicon area compared to a static comparator. This study is the first step towards a full fault tolerant approach targeting robustness improvement of CMOS logic circuits.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"297 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132762910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

An oscillation-based test structure for timing information extraction 一种基于振荡的时序信息提取测试结构

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231083

E. Jang, A. Gattiker, S. Nassif, J. Abraham

{"title":"An oscillation-based test structure for timing information extraction","authors":"E. Jang, A. Gattiker, S. Nassif, J. Abraham","doi":"10.1109/VTS.2012.6231083","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231083","url":null,"abstract":"Technology scaling introduces many sources of variability and uncertainty that are difficult to model and predict [3]. The result of these uncertainties is a degradation in our ability to predict the performance of fabricated chips, i.e., a lack of model-to-hardware matching. The prediction of circuit performance is the result of a complex hierarchy of models starting at the basic MOSFET device model and rising to full-chip models of important performance metrics like power, frequency of operation, etc. The assessment of the quality of such models is an important activity, but it is becoming harder and more complex with rising levels of variability, as well as with the increase in the number of systematic effects observed in modern CMOS processes. The purpose of this paper is to introduce a special-purpose test structure that specifically focuses on ensuring the accuracy of gate timing models. The certification of digital design correctness (the so-called signoff) is based largely on the results of performing a Static Timing Analysis (STA) [15], [18], which, in turn, is based entirely on the gate timing models. Our test structure compares favorably to alternative approaches; it is far easier to obtain the desired results than direct delay measurement, and it is much more general than simple ring oscillator structures. Further, the structure is specified at a high level, allowing it to be synthesized using a standard ASIC place-and-route flow, thus capturing the systematic local layout effects which can sometimes be lost by simpler (e.g., ring oscillator) structures. Experimental results show the structure can play an important role in identifying mismatches between timing models and observed hardware.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123278955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Delay test resource allocation and scheduling for multiple frequency domains 多频域延迟测试资源分配与调度

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231089

B. Arslan, A. Orailoglu

引用次数: 2

Dual-frequency incoherent subsampling driven test response acquisition of spectrally sparse wideband signals with enhanced time resolution 增强时间分辨率的频谱稀疏宽带信号的双频非相干次采样驱动测试响应采集

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231093

Nicholas Tzou, Thomas Moon, Xian Wang, H. Choi, A. Chatterjee

{"title":"Dual-frequency incoherent subsampling driven test response acquisition of spectrally sparse wideband signals with enhanced time resolution","authors":"Nicholas Tzou, Thomas Moon, Xian Wang, H. Choi, A. Chatterjee","doi":"10.1109/VTS.2012.6231093","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231093","url":null,"abstract":"In this paper, we propose a new test response acquisition technique for high-speed devices-based on dual-frequency incoherent sub-sampling and sparse signal reconstruction. The proposed technique enables reconstruction of spectrally sparse wideband signals such as multi-tone signals and short pseudo-random bit sequences (PRBS) with enhanced time/frequency resolution as opposed to current methods. The sampling hardware utilizes dual analog-to-digital converters (ADCs) and dedicated sampling frequency synthesizers with a common frequency reference. As compared to other compressive sampling architectures [1], the proposed hardware architecture is easy to implement at low cost since it does not require accurate sampling clock phase adjustment or random timing generation. For digital signal reconstruction, the proposed technique requires less number of waveform samples than conventional equivalent-time sampling techniques. In addition, the use of an resolution-enhanced discrete Fourier transform (DFT) frame and basis pursuit algorithms minimizes spectral leakage of incoherently sub-sampled signals. This co-design of sampling hardware and signal reconstruction algorithms enables testing of spectrally sparse wideband signals with enhanced time/frequency resolution.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132376095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Estimating Power Supply Noise and its impact on path delay 估计电源噪声及其对路径延迟的影响

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231066

S. K. Rao, C. Sathyanarayana, Ajay Kallianpur, R. Robucci, C. Patel

引用次数: 8

Low-cost high-speed pseudo-random bit sequence characterization using nonuniform periodic sampling in the presence of noise 在存在噪声的情况下，采用非均匀周期采样的低成本高速伪随机比特序列表征

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231094

Thomas Moon, Nicholas Tzou, Xian Wang, H. Choi, A. Chatterjee

引用次数: 7

Are advanced DfT structures sufficient for preventing scan-attacks? 高级DfT结构是否足以防止扫描攻击?

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231061

Jean DaRolt, G. D. Natale, M. Flottes, B. Rouzeyre

引用次数: 70

Test generation for subtractive specification errors 减法规范错误的测试生成

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231063

Patricia S. Lee, I. Harris

引用次数: 1

HBIST: An approach towards zero external test cost HBIST:实现零外部测试成本的方法

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231073

M. Bubna, K. Roy, A. Goel

{"title":"HBIST: An approach towards zero external test cost","authors":"M. Bubna, K. Roy, A. Goel","doi":"10.1109/VTS.2012.6231073","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231073","url":null,"abstract":"Test cost is increasingly becoming a major component of a product's design cost in scaled technologies. Exponential increase in test data volumes for sub-45 designs, especially for testing delay faults has led to large increase in ATE cost and test application time. In order to reduce external test cost, Logic BIST has been explored as a possible alternative to manufacturing test [1-5]. However, this paper shows that a large number of faults in BIST logic of large IWLS'05 and ITC'99 benchmark processors remain undetected after BIST run (42% of stuck-at and 34% of transition faults on average) and thus, BIST logic needs to be tested properly. This paper proposes a hierarchical BIST methodology `HBIST' which uses different BIST techniques to obtain complete stuck-at and transition fault coverage of CUT and then introduces additional levels of BIST logic to test for faults in the BIST logic at the preceding levels. A design methodology is proposed to optimize the number of additional levels of BIST required while keeping the BIST area and power overhead, and the addition of extra faults in BIST logic minimal. Experiments on large benchmarks show an average of 95.9% CUT stuck-at fault coverage (ATPG coverage of 96.4%) and 93.5% CUT transition fault coverage (ATPG coverage of 95.3%) is obtained using HBIST. Also, up to 99.2% (average 93.2%) reduction in external ATE test cost (including cost needed to test additional BIST levels) is obtained using two levels of BIST at 7% average area overhead (compared to scan overhead of 38.2%) and 18% increase in test power.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124300265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1