2012 IEEE 30th VLSI Test Symposium (VTS)最新文献_第3页

Smart selection of indirect parameters for DC-based alternate RF IC testing 智能选择基于直流的替代射频IC测试的间接参数

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231074

H. Ayari, F. Azaïs, S. Bernard, M. Comte, M. Renovell, V. Kerzérho, O. Potin, C. Kelma

引用次数: 37

Power Characterization of Embedded SRAMs for Power Binning 用于功率分组的嵌入式sram的功率特性

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231103

Yang Zhao, Lisa Grenier, Amitava Majumdar

引用次数: 4

Cost modeling and analysis for interposer-based three-dimensional IC 基于中间体的三维集成电路成本建模与分析

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231088

Ying-Wen Chou, Po-Yuan Chen, Mincent Lee, Cheng-Wen Wu

{"title":"Cost modeling and analysis for interposer-based three-dimensional IC","authors":"Ying-Wen Chou, Po-Yuan Chen, Mincent Lee, Cheng-Wen Wu","doi":"10.1109/VTS.2012.6231088","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231088","url":null,"abstract":"Three-dimensional (3D) integration has recently become a popular technology for integrated circuits (IC). 3D IC with the passive silicon interposer is currently the main trend in the industry, especially for processor-memory integration. Evaluating the economic efficiency of test operations in the interposer-based 3D IC thus is important. We propose a cost model for the Die-to-Wafer (D2W) and Die-to-Die (D2D) stacking, including manufacturing cost and test cost. A tool which is based on the proposed cost model is developed. We use this tool for cost analysis and for finding the most cost effective test flow. The results show that, in some applications, test flows including the iterative known-good stack (KGS) test and the pre-bond interposer test significantly reduce the cost, when the KGS test yield is lower than 98.2% and the pre-bond interposer test yield is lower than 99.38%. A Shmoo plot is depicted to show the lower bound of the yield of the final package level test, given the number of stacked dies and the final yield. For different applications, the proposed model evaluates the critical yield or cost values, which helps the designers to determine the most cost effective test flow and the system architecture.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131766110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Advanced test methods for SRAMs sram的先进测试方法

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231070

A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel

引用次数: 34

Test of phase interpolators in high speed I/Os using a sliding window search 使用滑动窗口搜索的高速I/ o相位插补器测试

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231092

J. Chun, Siew Mooi Lim, Shao Chee Ong, Jae Wook Lee, J. Abraham

引用次数: 0

Static test compaction for transition faults under the hazard-based detection conditions 基于危害检测条件下的过渡故障静态压实试验

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231099

I. Pomeranz

引用次数: 3

Silicon evaluation of faster than at-speed transition delay tests 硅评估比高速过渡延迟试验快

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231084

S. Chakravarty, Narendra Devta-Prasanna, A. Gunda, Junxia Ma, Fan Yang, H. Guo, R. Lai, D. Li

引用次数: 11

Write-through method for embedded memory with compression Scan-based testing 具有基于压缩扫描测试的嵌入式存储器的透写方法

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231096

Geewhun Seok, Hong Kim, B. Mohammad

引用次数: 3

An on-chip NBTI monitor for estimating analog circuit degradation 用于估计模拟电路退化的片上NBTI监视器

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231082

S. Askari, M. Nourani, Mini Rawat

{"title":"An on-chip NBTI monitor for estimating analog circuit degradation","authors":"S. Askari, M. Nourani, Mini Rawat","doi":"10.1109/VTS.2012.6231082","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231082","url":null,"abstract":"Negative Bias Temperature Instability (NBTI) degrades the life-time of both the analog and digital circuits significantly and has become a major concern in nanoscale regime. In analog circuits, the DC biasing voltage is always present irrespective of the input signal. Therefore, coupled with high operating temperature (due to digital switching and high packaging density of SoC) and constant DC bias there would be continuous NBTI stress in analog circuits with minor or almost no recovery. Moreover, mismatch and input referred offset voltage caused by NBTI in differential pairs, current sources and cascode stages can cause instantaneous failure or catastrophic failure after certain time period. The problem of NBTI is usually addressed by leaving large design margins or employing adaptive body bias/adaptive voltage scaling based calibration algorithms using on-chip sensors or monitors. We present an ultra low power and small area on-chip NBTI sensor which can be used for accurately sensing the NBTI degradation in analog circuits. We have shown that the temporal degradation in threshold voltage of pMOS transistor in analog circuits has high correlation to the variation of reference voltage of our NBTI sensor which can be exploited for accurate calibration of analog circuits. Measurement results are also provided for the proposed sensor fabricated in commercially available 65nm process.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128659960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Test generator with preselected toggling for low power built-in self-test 测试发电机预选切换低功率内置自检

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI: 10.1109/VTS.2012.6231071

J. Rajski, J. Tyszer, Grzegorz Mrugalski, B. Nadeau-Dostie

引用次数: 40