Write-through method for embedded memory with compression Scan-based testing

Abstract

Demands for low defects per million (DPM) rates are increasing as process technology scaling is able to increase transistor density and add more functionality to the integrated circuits. For stuck at fault and delay testing, Scan-based testing in conjunction with ATPG is the preferred approach to reduces DPM compared to functional testing. However embedded memories have been a challenge to ATPG gate level simulation due to limitation of gate level generation method and the additional logic needed to prevent unknowns (X's) to be propagated from memory during ATPG testing, this X-propagation becomes more of an issue when the design has a test compressor. This paper examines the challenges of ATPG memory write through method on the design with chip test compression logic and proposes new design strategy and ATPG pattern generation method. The proposed design will make the memory look like a one dimensional set of registers and ATPG pattern generation method will support write through mode without Xs propagation.