On the parametric failures of SRAM in a 3D-die stack considering tier-to-tier supply cross-talk

Abstract

This paper analyzes the supply crosstalk between logic cores and SRAMs on separate tiers in a 3D die-stack using a distributed RLC based 3D power grid model. The analysis shows that due to the supply cross-talk power variation in cores modulates the performances and parametric failures in SRAM.