Test algorithms for ECC-based memory repair in nanotechnologies

Abstract

In modern SoCs embedded memories should be repaired after fabrication to achieve acceptable yield. They should also be protected by ECC against field failures to achieve acceptable reliability. To avoid paying the area and power penalties of both approaches, we can use ECC to fix both fabrication and field failures. However, we show that efficient implementation of this approach may require special diagnosis hardware or new memory test algorithm that exhibit the so-called “single-read double-fault detection” property defined in this paper. We also propose test algorithms satisfying this property.