考虑层间电源串扰的3d芯片堆叠中SRAM的参数失效

2012 IEEE 30th VLSI Test Symposium (VTS) Pub Date : 2012-04-23 DOI:10.1109/VTS.2012.6231064

W. Yueh, S. Chatterjee, A. Trivedi, S. Mukhopadhyay

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引用次数: 3

摘要

本文采用基于分布式RLC的三维电网模型，分析了三维模堆中各层逻辑核与sram之间的电源串扰。分析表明，由于电源串扰，核内功率的变化会调制SRAM的性能和参数失效。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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On the parametric failures of SRAM in a 3D-die stack considering tier-to-tier supply cross-talk

This paper analyzes the supply crosstalk between logic cores and SRAMs on separate tiers in a 3D die-stack using a distributed RLC based 3D power grid model. The analysis shows that due to the supply cross-talk power variation in cores modulates the performances and parametric failures in SRAM.

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2012 IEEE 30th VLSI Test Symposium (VTS)

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