Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)最新文献_第3页

Low power chips: a fabless asic perspective 低功耗芯片:无晶圆厂基本视角

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1394013

S. Bhonge, V. Boppana

{"title":"Low power chips: a fabless asic perspective","authors":"S. Bhonge, V. Boppana","doi":"10.1145/1393921.1394013","DOIUrl":"https://doi.org/10.1145/1393921.1394013","url":null,"abstract":"Summary form only given. The fabless ASIC model has changed the landscape of ASIC design by offering a high-quality, cost-effective and open alternative to realizing ASICs. The very nature of this model (because of its reliance on the third-party foundry, IP ecosystem) offers unique challenges and opportunities for implementing low power chips. This tutorial presents an overview of the exciting low power challenges, opportunities and solutions available in a fabless ASIC model. We review state-of-the-art low power IC solutions and case studies from varied markets, including processor-based, wired, wireless, consumer and multi-core chips. We start with a discussion on technology trends and low power challenges. We next review the spectrum of low power solutions and identify the appropriate opportunities that are applicable to the fabless ASIC model. We also discuss unique technology solutions that employ the use of transistor-level transformations that extend the solutions typically available in the ASIC model. Next, we discuss how these solutions are deployed in the model. We finally present detailed case studies of ICs. The low power techniques employed in the ICs include selection of technology node/process, selection of macros, multi-voltage design, power gating, custom transistor-level circuits, clocking, selection and optimization of standard cell libraries, design/architecture and power planning, advanced timing and power optimization, low power design closure, innovative packaging and power impact on variability-tolerance. The tutorial arms the audience with the best techniques, tools and methodologies to achieve the lowest power Silicon for state-of-the-art ASICs.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116979475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Word-interleaved cache: an energy efficient data cache architecture 字交错缓存:一种节能的数据缓存架构

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393991

T. V. Kalyan, M. Mutyam

引用次数: 7

Penalty for power reduction -: performance or schedule or yield? 减少功率的惩罚:性能、进度还是产量?

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393999

B. Sarker, J. Ahuja, Arijit Dutta, D. Srinath, K. Sridhar, Radhakrishnan Nair, J. Lahiri

{"title":"Penalty for power reduction -: performance or schedule or yield?","authors":"B. Sarker, J. Ahuja, Arijit Dutta, D. Srinath, K. Sridhar, Radhakrishnan Nair, J. Lahiri","doi":"10.1145/1393921.1393999","DOIUrl":"https://doi.org/10.1145/1393921.1393999","url":null,"abstract":"It is often said \"It is always give and take\" and that \"there is no such thing as a free lunch\". The same would hold true for Low Power designs. The questions oft asked is What are the trade-offs for reduction in power? What would be the limits of power reduction, before it starts impacting other parameters? Designs are generally characterized by four predominant parameters - performance, timing, area and power. As design and manufacturing became different disciplines supported by independent teams, two additional parameters were added to the design characterization, schedule and yield. Schedule implies the time taken to get the design to the desired performance and yield indicates the percentage of designs that meet the performance criterion, after manufacturing. Performance, schedule and yield have become a proxy for the expertise built in the design team and the capability of the tools to handle the complex designs. Teams with expertise and access to appropriate tools, can build high performance designs faster and at the desired yields. Traditionally performance has been correlated with timing or the maximum operating frequency of the design. More recently power is becoming an important area of concern, and is forcing designers to design within the power specifications of the design. Power has been seen as limiting the timing performance for many designs. In this key panel, we will discuss: What could be some of the best practices to reduce power while maintaining timing performanceHow could one analyze the performance, schedule, yield trade-off with an exampleDiscuss industry-wide effort to reduce the penalty for further power reduction","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126763918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Innovations to extend CMOS nano-transistors to the limit 将CMOS纳米晶体管扩展到极限的创新

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393924

T. Ghani

{"title":"Innovations to extend CMOS nano-transistors to the limit","authors":"T. Ghani","doi":"10.1145/1393921.1393924","DOIUrl":"https://doi.org/10.1145/1393921.1393924","url":null,"abstract":"Summary form only given. The scaling of CMOS technology has led to phenomenal growth in transistor density and performance during the last three decades. However, starting at 90nm CMOS node, the industry started to experience significant barriers in achieving historical transistor performance gains through traditional dimensional scaling. Fortunately, the industry has responded positively to this challenge by implementing many innovations in device structure and materials to overcome traditional scaling barriers. Intel has been at the forefront in addressing these challenges by successfully driving transistor innovations from research phase to mainstream CMOS manufacturing. Implementation of uniaxial strained-silicon transistors at the 90nm node and the recently announced \"HiK+Metal Gate\" transistors for the 45nm node are two excellent examples of major innovations which have demonstrated dramatic performance enhancement. After a brief review highlighting the dramatic performance benefits demonstrated with uniaxial strained silicon technology, I will describe process details and present significant performance gains achieved with \"HiK+Metal Gate\" transistor technology for 45nm CMOS node. Finally, I will discuss the role of increasing power density and transistor parasitics in limiting future CMOS transistor scaling and describe potential new transistor structure and material innovations required to meet performance/power/density improvements beyond 45nm CMOS node. The convergence of new transistor structure and materials will be critical for successfully scaling CMOS transistors through next decade.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124167762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Instruction-driven clock scheduling with glitch mitigation 带有故障缓解的指令驱动时钟调度

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1394017

Gu-Yeon Wei, D. Brooks, A. Khan, Xiaoyao Liang

{"title":"Instruction-driven clock scheduling with glitch mitigation","authors":"Gu-Yeon Wei, D. Brooks, A. Khan, Xiaoyao Liang","doi":"10.1145/1393921.1394017","DOIUrl":"https://doi.org/10.1145/1393921.1394017","url":null,"abstract":"Instruction-driven clock scheduling is a mechanism that minimizes clock power in deeply-pipelined datapaths. Analysis of realistic processor workloads shows a preponderance of bubbles persist through pipelines like the floating point unit. Clock scheduling ostensibly adapts pipeline depth with respect to bubbles in the instruction stream without performance loss. Unfortunately, shallower pipelines (i.e. longer pipe stages) are prone to larger amounts of glitches propagating through logic, increasing dynamic power. Experimentally measured results from a 130 nm FPU test chip with flexible clocking capabilities show a super-linear increase in glitch-induced dynamic power for shallower pipelines. While higher glitch power can severely diminish the power savings offered by clock scheduling, judicious clocking of intermediate stages offers glitch mitigation to recover power savings for worst-case scenarios. Detailed analysis of clock scheduling applied to a FPU in a POWER4-like processor running realistic workloads shows an average net power savings of 15% compared to an aggressively clock-gated design.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122510224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes 针对IEEE 802.11n LDPC码的低功耗分层解码架构

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393989

Jie Jin, C. Tsui

引用次数: 10

Towards a green electronic world: a collaborative approach 迈向绿色电子世界:合作方法

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393922

J. Ahuja

引用次数: 1

Thermal analysis of 8-T SRAM for nano-scaled technologies 用于纳米技术的8-T SRAM热分析

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393953

M. Meterelliyoz, J. Kulkarni, K. Roy

引用次数: 10

Low-power high-accuracy timing systems for efficient duty cycling 低功耗高精度定时系统，高效占空比

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393943

T. Schmid, J. Friedman, Zainul Charbiwala, Young H. Cho, M. Srivastava

{"title":"Low-power high-accuracy timing systems for efficient duty cycling","authors":"T. Schmid, J. Friedman, Zainul Charbiwala, Young H. Cho, M. Srivastava","doi":"10.1145/1393921.1393943","DOIUrl":"https://doi.org/10.1145/1393921.1393943","url":null,"abstract":"Time keeping and synchronization are important services for networked and embedded systems. High quality timing information allows embedded network nodes to provide accurate time-stamping, fast localization, efficient duty cycling schedules, and other basic but essential functions - all of which are required for low power operation. In this paper we present a new type of local clock source called Crystal Compensated Crystal based Timer (XCXT) and a number of novel algorithms that effectively utilize it to achieve low power consumption in wireless sensor networks. The XCXT has timing accuracies similar to timers based on temperature compensated crystal oscillators (TCXO) but has a lower implementation cost and requires less power. Our initial 8 MHz prototype unit, using the simplest algorithm, achieves an effective frequency stability of ±1.2 ppm and consumes only 1.27 mW. On the other hand, commercially available TCXOs with similar stability can cost over 10 times as much and consume over 20 mW. In addition to the prototype, we will present algorithms that will improve the XCXT's power consumption by at least 48%, depending on application and environmental conditions. We will also show how XCXT's power efficiency can be improved even further by employing clocks at different frequency when different time granularities are required by an application.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114547151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Lazy instruction scheduling: keeping performance, reducing power 懒惰指令调度:保持性能，降低功耗

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1394020

A. Mahjur, M. Taghizadeh, A. Jahangir

引用次数: 1