{"title":"Towards a green electronic world: a collaborative approach","authors":"J. Ahuja","doi":"10.1145/1393921.1393922","DOIUrl":null,"url":null,"abstract":"Summary form only given. Increasing power density of complex SoC's have made low-power a topic of interest in the industry. Power considerations in portable and wireless consumer devices have become a key part of many product specifications. Even for wired devices and other industry segments in which battery power has not traditionally been an issue, considerations of packaging, reliability, and cooling costs brings power firmly to the forefront at smaller geometries. In particular, as designs migrate to sub-90 nm process nodes, power management becomes a serious concern across the entire design and manufacturing chain. To help design teams, there is a need to adopt advanced power reduction techniques, where a complete low power solution is needed for the design, verification, and implementation of low-power chips. Since the challenge spans across the design chain, industry collaboration is an imperative.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"605 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1393921.1393922","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Summary form only given. Increasing power density of complex SoC's have made low-power a topic of interest in the industry. Power considerations in portable and wireless consumer devices have become a key part of many product specifications. Even for wired devices and other industry segments in which battery power has not traditionally been an issue, considerations of packaging, reliability, and cooling costs brings power firmly to the forefront at smaller geometries. In particular, as designs migrate to sub-90 nm process nodes, power management becomes a serious concern across the entire design and manufacturing chain. To help design teams, there is a need to adopt advanced power reduction techniques, where a complete low power solution is needed for the design, verification, and implementation of low-power chips. Since the challenge spans across the design chain, industry collaboration is an imperative.