Innovations to extend CMOS nano-transistors to the limit

Abstract

Summary form only given. The scaling of CMOS technology has led to phenomenal growth in transistor density and performance during the last three decades. However, starting at 90nm CMOS node, the industry started to experience significant barriers in achieving historical transistor performance gains through traditional dimensional scaling. Fortunately, the industry has responded positively to this challenge by implementing many innovations in device structure and materials to overcome traditional scaling barriers. Intel has been at the forefront in addressing these challenges by successfully driving transistor innovations from research phase to mainstream CMOS manufacturing. Implementation of uniaxial strained-silicon transistors at the 90nm node and the recently announced "HiK+Metal Gate" transistors for the 45nm node are two excellent examples of major innovations which have demonstrated dramatic performance enhancement. After a brief review highlighting the dramatic performance benefits demonstrated with uniaxial strained silicon technology, I will describe process details and present significant performance gains achieved with "HiK+Metal Gate" transistor technology for 45nm CMOS node. Finally, I will discuss the role of increasing power density and transistor parasitics in limiting future CMOS transistor scaling and describe potential new transistor structure and material innovations required to meet performance/power/density improvements beyond 45nm CMOS node. The convergence of new transistor structure and materials will be critical for successfully scaling CMOS transistors through next decade.