Thermal analysis of 8-T SRAM for nano-scaled technologies

M. Meterelliyoz, J. Kulkarni, K. Roy
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引用次数: 10

Abstract

Different sections of a cache memory may experience different temperature profiles depending on their proximity to other active logic units such as the execution unit. In this paper, we perform thermal analysis of cache memories under the influence of hot-spots. In particular, 8-T SRAM bit cell is chosen because of its robust functionality at nano-scaled technologies. Thermal map of entire 8-T SRAM cache is generated using hierarchical compact thermal models while solving the leakage and temperature self consistently. The impact of spatial temperature variations on 8T-SRAM parameters such as local bitline (LBL) sensing delay, noise robustness and bitcell stability are evaluated for 45nm/32nm/22nm bulk CMOS technology nodes. The effectiveness of variable keeper sizing on LBL sensing delay is analyzed. It is predicted that at 22 nm node, the leakage induced temperature rise has severe effects on the 8-T SRAM characteristics.
用于纳米技术的8-T SRAM热分析
缓存存储器的不同部分可能会经历不同的温度曲线,这取决于它们与其他活动逻辑单元(如执行单元)的接近程度。本文对热点影响下的高速缓存存储器进行了热分析。特别是,选择8-T SRAM位单元是因为它在纳米级技术上具有强大的功能。采用分层紧凑热模型生成整个8-T SRAM缓存的热图,同时解决了泄漏和温度自一致问题。在45nm/32nm/22nm块体CMOS技术节点上,评估了空间温度变化对8T-SRAM参数(如本地位线(LBL)传感延迟、噪声鲁棒性和位单元稳定性)的影响。分析了可变守门员尺寸对LBL感知延迟的影响。预测在22 nm节点,泄漏引起的温升会严重影响8-T SRAM的特性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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