Low power chips: a fabless asic perspective

Abstract

Summary form only given. The fabless ASIC model has changed the landscape of ASIC design by offering a high-quality, cost-effective and open alternative to realizing ASICs. The very nature of this model (because of its reliance on the third-party foundry, IP ecosystem) offers unique challenges and opportunities for implementing low power chips. This tutorial presents an overview of the exciting low power challenges, opportunities and solutions available in a fabless ASIC model. We review state-of-the-art low power IC solutions and case studies from varied markets, including processor-based, wired, wireless, consumer and multi-core chips. We start with a discussion on technology trends and low power challenges. We next review the spectrum of low power solutions and identify the appropriate opportunities that are applicable to the fabless ASIC model. We also discuss unique technology solutions that employ the use of transistor-level transformations that extend the solutions typically available in the ASIC model. Next, we discuss how these solutions are deployed in the model. We finally present detailed case studies of ICs. The low power techniques employed in the ICs include selection of technology node/process, selection of macros, multi-voltage design, power gating, custom transistor-level circuits, clocking, selection and optimization of standard cell libraries, design/architecture and power planning, advanced timing and power optimization, low power design closure, innovative packaging and power impact on variability-tolerance. The tutorial arms the audience with the best techniques, tools and methodologies to achieve the lowest power Silicon for state-of-the-art ASICs.