{"title":"Improved high-temperature dielectric property of epoxy resin composites with nano- and micro-sized magnesia fillers","authors":"Q. Xie, Y. Ohki, N. Hirai, Y.H. Cheng","doi":"10.1109/IWIPP.2017.7936745","DOIUrl":"https://doi.org/10.1109/IWIPP.2017.7936745","url":null,"abstract":"Nano-sized magnesium oxide or magnesia has been reported to be useful for suppressing the space charge accumulation when it is added in epoxy resin. However, the addition of nano-magnesia to epoxy resin decreases the glass transition temperature (Tg) signficantly, which may limit industrial applications of magnesia/epoxy nanocomposites. In this work, nanomagnesia particles with an average size of 52 nm and micro-magnesia with an average size of 3.1 pm were mixed in a commercially available bisphenol-A epoxy resin. The weight ratio of nano- and micro-fillers in each composite was changed, while the total content of the two fillers was fixed at 5 weight%. As a result, it has become clear that the addition of micro-sized magnesia fillers to magnesia/epoxy nanocomposites recovers Tg back to its original high temperature. Then, a dc electric field of 30 kV/mm was applied to the samples for 20 minutes at various temperatures from 40 to 200 °C and space charge distributions were measured by the pulsed electro-acoustic method. The results show that space charge accumulates in both vicinities of the cathode and the anode with the same polarities as those of the nearby electrodes when the temperature is 80 °C or below. However, space charges become hetero and are observed only in the vicinity of the cathode at 140 °C and above. These homocharges and heterocharges become very small when the weight content of nano-sized fillers increases, which is industrially very important. Both complex dielectric permittivity and electrical conductivity also decrease with the increase in the content of nanofillers.","PeriodicalId":164552,"journal":{"name":"2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123438450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Advanced double sided cooling IGBT module and power control unit development","authors":"Shiwu Zhu, Yun Li, Yangang Wang, Yaqing Ma, Chundong Wu, Mingliang Jiao, Zhenlong Zhao, Jun Yu","doi":"10.1109/IWIPP.2017.7936750","DOIUrl":"https://doi.org/10.1109/IWIPP.2017.7936750","url":null,"abstract":"This paper presents an Integrated Power Module (IPM) and an Integrated Power Unit (IPU) which are based on the IGBT double sided cooling technology. The IPU can be used as the motor control inverter in the electric vehicle. While the IPM used in the IPU is packaged with latest 650V trench field-stop IGBT device and double sided cooling technology. With the double sided soldering and cooling technology, traditional aluminum wire bonds have been eliminated. Reliability and thermal performance of the module are greatly improved. Compared with the traditional single sided cooling module, thermal resistance has been reduced by 23%. Equipped with the active gate driver technology, power losses of the IPM have been greatly optimized. Operation of IPU system with battery voltage 450V and output phase current 450Arms has been achieved.","PeriodicalId":164552,"journal":{"name":"2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)","volume":"114 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114087006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Saijun Mao, Chengmin Li, Tingting Song, J. Popovic, J. Ferreira
{"title":"High frequency high voltage generation with air-core transformer","authors":"Saijun Mao, Chengmin Li, Tingting Song, J. Popovic, J. Ferreira","doi":"10.1109/IWIPP.2017.7936761","DOIUrl":"https://doi.org/10.1109/IWIPP.2017.7936761","url":null,"abstract":"A novel high frequency high voltage (HV) generator circuit with air-core transformer is proposed in this paper to achieve high power density packaging structure and compact size advantages. Planar multi-layer printed circuit board(PCB) winding and litz wire wound winding structure are investigated for air-core HV transformer. The electrical design of air-core HV transformer with HV multiplier circuit based on 1.2kV SiC Schottky diode are introduced. A with 450 kHz switching frequency HV generator prototype with 310W output power and 1kV output voltage is built in lab. The litz wire air-core HV transformer prototype is built to compare the efficiency, thermal performance and size with planar air-core HV transformer. The planar PCB air-core transformer based on HV generator can achieve 80.5% efficiency and 1.09kW/L power density. The litz wire wounded transformer based HV generator provide 89.0% efficiency and around 0.53kW/L power density. The design with planar PCB air-core transformer enable high voltage generation circuit system compact planar packaging. The design with litz wire air-core HV transformer behaves higher efficiency and thermal performance with low high frequency AC winding loss.","PeriodicalId":164552,"journal":{"name":"2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116827816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Suppression of electromagnetic interference using screening and shielding techniques within the switching cells","authors":"Zhe Zhang, C. Mark Johnson","doi":"10.1109/IWIPP.2017.7936762","DOIUrl":"https://doi.org/10.1109/IWIPP.2017.7936762","url":null,"abstract":"In this paper we introduce the use of combination of screening and shielding to suppress electromagnetic interference (EMI) generated by a switching cell. We investigate the screening of common mode (CM) currents and the shielding of magnetic fields generated by a model switching cell using a combination of simulation tools and measurements. Simulation results align with measurements very well up to 100MHz, confirming that a relatively simple model can be used to investigate different arrangements of screen layer. We demonstrate that electromagnetically coupled currents produced by rapidly changing voltages and currents in the main switching circuit can be circulated back to the local DC-link or absorbed rather than being coupled to the external environment.","PeriodicalId":164552,"journal":{"name":"2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115017301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and construction of a co-planar power bus interconnect for low inductance switching","authors":"Xi Lin, Jianfeng Li, Mark C. Johnson","doi":"10.1109/IWIPP.2017.7936755","DOIUrl":"https://doi.org/10.1109/IWIPP.2017.7936755","url":null,"abstract":"A co-planar tab-slot type of interconnect demonstrator for connecting power switching devices and DC bus capacitors has been designed and constructed, aimed at low inductance switching. The demonstrator is composed of a double-sided tab connector and a dual polarity slot. This type of interconnect eliminates the use of screw terminal connection between a power module and the DC bus as well as between the DC bus and power capacitors, thus serves to maintain a coplanar current profile throughout the power distribution path. Parasitic analysis both in impedance testing and in Finite Element simulation suggests that the inductance in the bus loop of the demonstrator is approximately half of that achieved in an equally dimensioned busbar with conventional screw terminals.","PeriodicalId":164552,"journal":{"name":"2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122258957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Z. Toth-Pal, Yafan Zhang, T. Hammam, H. Nee, M. Bakowski
{"title":"Thermal improvement of press-pack packages: Pressure dependent thermal contact resistance with a thin silver interlayer between molybdenum substrate and silicon carbide chip","authors":"Z. Toth-Pal, Yafan Zhang, T. Hammam, H. Nee, M. Bakowski","doi":"10.1109/IWIPP.2017.7936753","DOIUrl":"https://doi.org/10.1109/IWIPP.2017.7936753","url":null,"abstract":"In typical press-pack, free-floating packages the thermal contact resistance between chip and substrate is a major limiting factor for the cooling ability of the power module. We report an introduction of a new, thin Silver interlayer between Molybdenum substrate and chip, and how it improves the thermal contact. The thermal contact resistances were measured with and without a Silver interlayer at different pressures. The surface roughness of the SiC chip and the Molybdenum substrate were characterized. The thermal contact resistances were measured at three different heating power levels. The results show a significant reduction of the thermal contact resistance with only a few micrometer Silver interlayer. The improved cooling effect of a Silver interlayer was also demonstrated with a fluid dynamics type of 3 D simulation comparing temperature distributions with and without a Silver interlayer. These results project a possible thermal improvement in press-pack packages.","PeriodicalId":164552,"journal":{"name":"2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130641218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reducing thermal coupling using fluid cooled low-k interposers","authors":"M. Fish, P. McCluskey, A. Bar-Cohen","doi":"10.1109/IWIPP.2017.7936769","DOIUrl":"https://doi.org/10.1109/IWIPP.2017.7936769","url":null,"abstract":"The thermal isolation capabilities of fluid cooled via-enhanced glass interposers are investigated with resistive-heater test chips and IR thermography. Previous studies have shown that the degree of thermal coupling between adjacent devices hosted on via-enhanced low conductivity interposers is lower than those on silicon interposers, but at the cost of increased chip-to-ambient thermal resistance. By integrating the enhanced low-k interposer with an embedded microgap cooler, much higher chip power can be dissipated while maintaining an acceptable temperature rise.","PeriodicalId":164552,"journal":{"name":"2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)","volume":"526 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114088992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis of quasi-Z source PFC convertor and its comparison with traditional flyback","authors":"Fahad M. Alhuwaishel, SinanAl-Obaidi, N. Ahmed","doi":"10.1109/IWIPP.2017.7936758","DOIUrl":"https://doi.org/10.1109/IWIPP.2017.7936758","url":null,"abstract":"The quasi Z-source power factor correction (QZS-PFC) in the range of 36–720W is analyzed for continuous conduction mode operation and compared with a classical flyback power factor correction (F-PFC) under the same operation conditions. A very precise closed loop duty ratio control was developed to optimize the performance of the QZS-PFC. The selected topology of QZS-PFC is compared with traditional F-PFC operating in continuous conduction mode (CCM) and the study confirms that it operates better than the F-PFC at different power ratings. The major advantage of QZS-PFC is its high performance, and ability to accommodate higher load than the traditional F-PFC. The total harmonic distortion (THD) for the QZS-PFC was considerably low when load were increasing; the value for the THD% reached the standardized limits of 5% while operation at load of 360 W and above. Moreover, the power factor value is close to one across the range of operation with minimal voltage and current ripple. It was confirmed that the main elements of QZS-PFC has lower current and voltage stress due to the effect of crossed capacitors. In contrast, F-PFC suffers from high voltage spikes and requires a snubber circuit. Considering the obtained results, the QZS-PFC has a better operation range which makes it an interesting topology to be widely explored.","PeriodicalId":164552,"journal":{"name":"2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116281881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Lifetime prediction of viscoplastic lead-free solder: A new solder material, SACQ","authors":"Tung Ching Lui","doi":"10.1109/IWIPP.2017.7936754","DOIUrl":"https://doi.org/10.1109/IWIPP.2017.7936754","url":null,"abstract":"The wafer level chip scale package (WLCSP) offers small form factor and high performance solution. Lately, a novel solder material, SACQ (92.443Sn4.0Ag0.5Cu8.0Bi0.05Ni 0.007Ge), is developed and applied on the WLCSP products but there is not much information and research in the nowadays market regarding the reliability of solder joints. This paper, lead-free solder constitutive laws of Anand's viscoplasticity model is utilized in the finite element method (FEM) calculation. The fatigue parameters of SACQ are presented and used to predict the characterized life cycle.","PeriodicalId":164552,"journal":{"name":"2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121379619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Akihiro Imakiire, Keigo Nakamura, H. Tanabe, Hikaru Kaisyakuji, Tomohiro Kubo, M. Kozako, M. Hikita
{"title":"Investigation of prototype SiC power module structure for low inductance and high heat operation","authors":"Akihiro Imakiire, Keigo Nakamura, H. Tanabe, Hikaru Kaisyakuji, Tomohiro Kubo, M. Kozako, M. Hikita","doi":"10.1109/IWIPP.2017.7936767","DOIUrl":"https://doi.org/10.1109/IWIPP.2017.7936767","url":null,"abstract":"This paper deal with structure for low inductance and high heat operation of silicon carbide (SiC) power module, which attracts attention in terms of high withstand voltage, high efficiency and high heat operation in recent years. First, the parasitic inductance of the power module of two types of structure; a conventional structure which forms the current path in a planar manner and a structure formed three-dimensionally is investigated using electromagnetic field analysis. In addition, thermal resistance of two types of power modules are experimentally evaluated from heat radiation performance. Experimental and simulated results reveals that the three-dimensionally formed power module is superior in the current path, resulting in lower parasitic inductance as well as smaller switching loss. Moreover, on state resistance and leakage current are evaluated at the junction temperature of 250 °C and the problems of power module package under high temperature environment is also investigated.","PeriodicalId":164552,"journal":{"name":"2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123824446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}