{"title":"使用流体冷却的低k介电剂减少热耦合","authors":"M. Fish, P. McCluskey, A. Bar-Cohen","doi":"10.1109/IWIPP.2017.7936769","DOIUrl":null,"url":null,"abstract":"The thermal isolation capabilities of fluid cooled via-enhanced glass interposers are investigated with resistive-heater test chips and IR thermography. Previous studies have shown that the degree of thermal coupling between adjacent devices hosted on via-enhanced low conductivity interposers is lower than those on silicon interposers, but at the cost of increased chip-to-ambient thermal resistance. By integrating the enhanced low-k interposer with an embedded microgap cooler, much higher chip power can be dissipated while maintaining an acceptable temperature rise.","PeriodicalId":164552,"journal":{"name":"2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)","volume":"526 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Reducing thermal coupling using fluid cooled low-k interposers\",\"authors\":\"M. Fish, P. McCluskey, A. Bar-Cohen\",\"doi\":\"10.1109/IWIPP.2017.7936769\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The thermal isolation capabilities of fluid cooled via-enhanced glass interposers are investigated with resistive-heater test chips and IR thermography. Previous studies have shown that the degree of thermal coupling between adjacent devices hosted on via-enhanced low conductivity interposers is lower than those on silicon interposers, but at the cost of increased chip-to-ambient thermal resistance. By integrating the enhanced low-k interposer with an embedded microgap cooler, much higher chip power can be dissipated while maintaining an acceptable temperature rise.\",\"PeriodicalId\":164552,\"journal\":{\"name\":\"2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)\",\"volume\":\"526 \",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWIPP.2017.7936769\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWIPP.2017.7936769","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reducing thermal coupling using fluid cooled low-k interposers
The thermal isolation capabilities of fluid cooled via-enhanced glass interposers are investigated with resistive-heater test chips and IR thermography. Previous studies have shown that the degree of thermal coupling between adjacent devices hosted on via-enhanced low conductivity interposers is lower than those on silicon interposers, but at the cost of increased chip-to-ambient thermal resistance. By integrating the enhanced low-k interposer with an embedded microgap cooler, much higher chip power can be dissipated while maintaining an acceptable temperature rise.