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Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium最新文献

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Electrical design considerations for high-speed computer packages 高速计算机封装的电气设计注意事项
Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium Pub Date : 1991-06-12 DOI: 10.1109/UGIM.1991.148161
M. Cases
{"title":"Electrical design considerations for high-speed computer packages","authors":"M. Cases","doi":"10.1109/UGIM.1991.148161","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148161","url":null,"abstract":"Wiring rules are required for high-speed logic circuits. They ensure proper operation of the receivers connected at any point on the transmission lines, and they guarantee the integrity of the delay equations used to predict the system performance. These wiring rules are strongly dependent on the driver characteristics and the system design requirements. It is important to develop a rule for maximum stub length to avoid excessive oscillations and long decaying time constants on the main line, which compromise system performance. The algorithms and procedures outlined greatly facilitate the developing of net delay equations for a high-speed package technology with various net types without sacrificing accuracy. The fundamental tradeoffs between the wiring rules, the signal quality, the number of delay equations, and the magnitude of their approximation error are discussed.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122093243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Oxidation and thermal stability of thin film copper layers 铜薄膜层的氧化和热稳定性
Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium Pub Date : 1991-06-12 DOI: 10.1109/UGIM.1991.148152
Y. Shacham-Diamand, J. Li, J.O. Olowlafe, S. Russel, Y. Tamou, J. Mayer
{"title":"Oxidation and thermal stability of thin film copper layers","authors":"Y. Shacham-Diamand, J. Li, J.O. Olowlafe, S. Russel, Y. Tamou, J. Mayer","doi":"10.1109/UGIM.1991.148152","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148152","url":null,"abstract":"The authors present several aspects of the thermal stability of thin-film copper layers. The copper oxidation experiment and the copper reaction with silicon and barrier layers were conducted separately. Copper oxidation has been characterized and its seems to be a major source of reliability problems. A qualitative model can be assigned to the copper oxidation which assumes an initial Cu/sub 2/O growth at random sites. The coalescence of those sites to form an oxide layer occurs after certain time. The formed oxide may limit the oxidation to the underlying copper and the process becomes diffusion controlled. At high temperatures (>255 degrees C) the oxide nucleation consumes most of the copper layer and no diffusion regime is observed. TiN, Cr, and Co were found to be non-reacting at typical processing temperatures. TiN seems to be superior since it does not react with copper and even at 550 degrees C.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117193329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A joint industry-university CIM project for university microelectronics manufacturing 大学微电子制造的产学研联合CIM项目
Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium Pub Date : 1991-06-12 DOI: 10.1109/UGIM.1991.148117
L. Fuller, C. Karacal, T. Vandenbosch, Steve Slagsvol, M. Poponiak
{"title":"A joint industry-university CIM project for university microelectronics manufacturing","authors":"L. Fuller, C. Karacal, T. Vandenbosch, Steve Slagsvol, M. Poponiak","doi":"10.1109/UGIM.1991.148117","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148117","url":null,"abstract":"A student-operated factory for manufacturing integrated circuits has been in operation at the Rochester Institute of Technology (RIT) since 1987. In 1989 RIT and IBM joined together to improve the factory operation by installing a computer-integrated manufacturing (CIM) system. The CIM system allows users control equipment access, monitor equipment status, do lot tracking, provide detailed current operator instructions, provide a paperless manufacturing environment, do scheduling, do manual input and auto input data collection, do statistical process control, do materials planning, download recipes to equipment, and realize feedback and feedforward control. Reports are routinely generated. The project is mostly completed and has proven to be successful in reducing cycle time, improving manufacturing flexibility, and increasing the quality of the devices manufactured at RIT.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132454253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Improving semiconductor yields by varying silicon substrate parameters 通过改变硅衬底参数来提高半导体产量
Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium Pub Date : 1991-06-12 DOI: 10.1109/UGIM.1991.148137
S. Weisbrod, D. Adelman, W. Huber
{"title":"Improving semiconductor yields by varying silicon substrate parameters","authors":"S. Weisbrod, D. Adelman, W. Huber","doi":"10.1109/UGIM.1991.148137","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148137","url":null,"abstract":"An experiment to determine the impact on wafer probe and fabrication yields of systematically varying silicon substrate parameters within current specification ranges is discussed. The effect of parametric splits of three relevant silicon parameters on device probe yields were investigated. The parameters that were chosen were resistivity, interstitial oxygen content, and backside condition of p-type silicon wafers with a","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133553262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low dielectric constant interconnect technology-a paradigm for interdisciplinary industry-university programs 低介电常数互连技术-跨学科产业-大学计划的范例
Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium Pub Date : 1991-06-12 DOI: 10.1109/UGIM.1991.148116
R. Gutmann, R. Isaac
{"title":"Low dielectric constant interconnect technology-a paradigm for interdisciplinary industry-university programs","authors":"R. Gutmann, R. Isaac","doi":"10.1109/UGIM.1991.148116","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148116","url":null,"abstract":"A multidisciplinary vertically integrated and professional-interactive industry-university research program is described. Unique features of the program include joint definition (and guidance) of research directions and priorities, extensive interactions between university and industry researchers within similar disciplines, and extensive on-campus interaction between the disciplines involved. While the research program in ongoing, the authors believe that the successful interactions and research results to date indicate that a new paradigm for sizably scaled interdisciplinary industry-university programs is being established.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132073479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast-turn IC prototyping for university education and research 用于大学教育和研究的快速集成电路原型设计
Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium Pub Date : 1991-06-12 DOI: 10.1109/UGIM.1991.148119
D. Cunningham, R. Gold
{"title":"Fast-turn IC prototyping for university education and research","authors":"D. Cunningham, R. Gold","doi":"10.1109/UGIM.1991.148119","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148119","url":null,"abstract":"The Massachussetts Microelectronics Center (M/sup 2/C) has recently completed the start-up of an IC fabrication facility for use by its eleven member universities. The primary mission of this facility is to produce prototypes of student-designed full-custom CMOS ICs on a fast-turn basis (i.e. 4 weeks or less), in order for students to test circuits they have designed within the normal time-frame of university courses. The M/sup 2/C fabrication facility is fundamentally different from a traditional high-volume manufacturing operation. Although many different designs are produced, the quantity of chips needed for any given design is quite small. The facility's critical measure of performance is cycle time, but because of cost constraints, it has minimal equipment redundancy and a very small engineering and production staff, compared to normal industry standards. A comprehensive operational strategy has been implemented to address this challenge, and packaged chips from recent multiproject wafer lots have been returned to students as quickly as 13 calendar days after design submission.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126608775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new approach to statistical process control in a test environment: the empirical delta control chart 测试环境中统计过程控制的新方法:经验δ控制图
Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium Pub Date : 1991-06-12 DOI: 10.1109/UGIM.1991.148134
S. Weisbrod, C. S. McFarland
{"title":"A new approach to statistical process control in a test environment: the empirical delta control chart","authors":"S. Weisbrod, C. S. McFarland","doi":"10.1109/UGIM.1991.148134","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148134","url":null,"abstract":"Past attempts at Harris Semiconductor to control the test measurements process and their inherent weaknesses are discussed. The empirical delta control chart (ED-chart), along with its corresponding control unit/die philosophy, is introduced as an alternative toward controlling the semiconductor wafer and package test environments. Only one control chart (per test parameter tracked) is required for all control units and die, as opposed to one chart for each unit or die. To add to this, no modification of the control limits is required when new control devices are introduced to the system. Their low chart count and their ability to stay with one set of charts solves many of the maintenance problems typically associated with statistical process control (SPC) in a test area. The permanent nature of an ED-chart representing one continuing standard facilitates the idea of continuous improvement. ED-charts emphasize the measurement aspect of a test area-where the ability to test accurately and repeatability over time are the goal.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115707582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A subthreshold model for the analysis of MOS IC's 用于MOS集成电路分析的亚阈值模型
Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium Pub Date : 1991-06-12 DOI: 10.1109/UGIM.1991.148144
M. El-Nokali, A. Afzali-Kushaa
{"title":"A subthreshold model for the analysis of MOS IC's","authors":"M. El-Nokali, A. Afzali-Kushaa","doi":"10.1109/UGIM.1991.148144","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148144","url":null,"abstract":"An accurate and computationally efficient charge-based model for the intrinsic capacitances in MOS transistors is proposed. The model is valid in the subthreshold regime, and is based on the quasi-static approximation. By integrating this model with a corresponding one in the strong inversion regime, a complete model valid in all regions of operation is presented. An interpolation scheme which guarantees the continuity of the drain current and the capacitances as well as their derivatives is used to provide a smooth transition from subthreshold to strong inversion.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"298 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114571821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Capacitance-voltage characteristics of amorphous silicon based metal-insulator-semiconductor structure 非晶硅基金属-绝缘体-半导体结构的电容-电压特性
Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium Pub Date : 1991-06-12 DOI: 10.1109/UGIM.1991.148130
J.S. Choi, G. Neudeck
{"title":"Capacitance-voltage characteristics of amorphous silicon based metal-insulator-semiconductor structure","authors":"J.S. Choi, G. Neudeck","doi":"10.1109/UGIM.1991.148130","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148130","url":null,"abstract":"A capacitance-voltage model for the a-Si:H-based metal-insulator-semiconductor (MIS) structure is presented, along with an alternative direct measurement method. The C-V model is based on the static I-V model developed using the simplified CFO band model for the a-Si bulk band gap states and the simplified Davis-Mott model for the surface states. The frequency variation of the measured admittance, using a somewhat modified thin-film transistor (TFT), is also modeled with the lateral flow transmission line model. These models can be used to monitor TFT-fabrication parameters and to extract accurate capacitance model parameters.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"73 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131967977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrical characterization of polysilicon surface roughness in double polysilicon EPROMS 双多晶硅eprom中多晶硅表面粗糙度的电学表征
Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium Pub Date : 1991-06-12 DOI: 10.1109/UGIM.1991.148126
R. Turkman
{"title":"Electrical characterization of polysilicon surface roughness in double polysilicon EPROMS","authors":"R. Turkman","doi":"10.1109/UGIM.1991.148126","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148126","url":null,"abstract":"Data retention in floating gate double-polysilicon erasable programmable read-only memories (EPROMs) strongly depends on the insulating properties of the interpolyoxide layer. The author describes a method for rapid evaluation of the interpolyoxide quality and the surface texture of the underlying polysilicon by simple electrical measurements. First, the electrical conduction mechanism in the interpolyoxide is discussed. A simple quantitative model relating the increased conductivity of polyoxides to the polysilicon surface morphology is presented. The test structures used in this study, the interpolyoxide conductivity measurements, and the proposed characterization technique are described. The results are discussed, and the predicted poly surface roughness is compared to that obtained by transmission electron microscopy (TEM).<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"319 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132184391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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