Capacitance-voltage characteristics of amorphous silicon based metal-insulator-semiconductor structure

Abstract

A capacitance-voltage model for the a-Si:H-based metal-insulator-semiconductor (MIS) structure is presented, along with an alternative direct measurement method. The C-V model is based on the static I-V model developed using the simplified CFO band model for the a-Si bulk band gap states and the simplified Davis-Mott model for the surface states. The frequency variation of the measured admittance, using a somewhat modified thin-film transistor (TFT), is also modeled with the lateral flow transmission line model. These models can be used to monitor TFT-fabrication parameters and to extract accurate capacitance model parameters.<>