{"title":"EUROSYSTEMS-an industry/university advanced system design education project","authors":"P. Pochmuller, M. Glesner, P. Windirsch","doi":"10.1109/UGIM.1991.148114","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148114","url":null,"abstract":"Gives an overview on the activities planned within the EUROSYSTEMS advanced microelectronics system design project. The main objective of the project is to bring microelectronic system solutions into the world of system designers from small and medium sized companies, as well as universities. This can only be achieved with the use of advanced silicon compilation tools. The authors describe how the EUROSYSTEMS project is embedding into a whole framework of other European Community programs like JESSI SMI, EuroPACE, COMMETT, EUROCHIP, ASCIS, etc. and the the interactions between these programs.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122411068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. J. Joyce, R.D. Alderman, T. P. Djeu, J.C. Smith
{"title":"A review of a statistical tool set for the yield enhancement of integrated circuits","authors":"R. J. Joyce, R.D. Alderman, T. P. Djeu, J.C. Smith","doi":"10.1109/UGIM.1991.148136","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148136","url":null,"abstract":"The authors describe a system that Harris Semiconductor has developed to aid in the analysis of circuit failures and predictions of functional yeilds. This system is based on a relational database in conjunction with the application of statistical tools. The core of the system is the relational database that uses the commercially available INGRES software. The system design is reviewed along with the supporting software and hardware tools used to create a tool box for yield analysis. Given the current levels of sophistication involved in manufacturing semiconductors, the flexibility of a relational database coupled with the correct analytical and statistical tools provides a powerful system for a yield enhancement resource.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"589 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122848115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electrical characterization of MOSIS-fabricated circuit elements","authors":"C. M. Stillo, R. Fox, D. Langford, D. J. Ferris","doi":"10.1109/UGIM.1991.148131","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148131","url":null,"abstract":"SPICE parameters and other data useful for analog design were determined for the MOSIS 2 mu m-double-metal double-poly p-well process. The channel-length modulation parameter LAMBDA and noise parameter KF were extracted for various sizes of n- and p-type MOSFETs with poly1 and poly2 gates. the zero-bias threshold voltage, bulk threshold parameters, saturation transconductance, lateral diffusion, and width correction of poly2 transistors were extracted. A vertical bipolar transistor is characterized.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132699164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"CAPE-VLSI implementation of a systolic processor array: architecture, design and testing","authors":"N. D. Hemkumar, K. Kota, Joseph R. Cavallaro","doi":"10.1109/UGIM.1991.148123","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148123","url":null,"abstract":"The singular value decomposition (SVD) is an important matrix factorization used in a variety of applications. The SVD exhibits better numerical stability due to the insensitivity to ill-conditioning or rank deficiency of matrices. However, the SVD is computationally intensive. The CORDIC array processor element (CAPE) is a single chip VLSI implementation of a processor element for the Brent-Luk-VanLoan systolic array which computes the SVD of a real matrix. The array utilizes CORDIC (coordinate rotation digital computer) arithmetic to perform the vector rotations and inverse tangent calculations in hardware. A six-chip prototype of the processor has been implemented as TinyChips using the MOSIS fabrication service. Experienced gain from designing the prototype helped in the design of integrated single-chip version. The chip has been implemented on a 5600*6900 mu die in a 2 mu n-well scalable CMOS process.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"57 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134135935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Clearinghouse for undergraduate microelectronics education: what have we learned?","authors":"B. MacDonald, D. Cunningham, R. Gold","doi":"10.1109/UGIM.1991.148113","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148113","url":null,"abstract":"The Massachusetts Microelectronics Center (M/sup 2/C), with support from the National Science Foundation, has established the Clearinghouse for Undergraduate Microelectronics Education (CUME) to support VLSI education programs at universities throughout the United States. The primary objective of CUME has been to increase the number of microelectronics education programs in the United States via a rapid start-up or bootstrap method. One year into the program, 20 universities have joined, and M/sup 2/C has identified several important trends in VLSI education as well as issues related to providing multi-platform software support to remote sites. The authors discuss those trends and issues, making some recommendations for future national programs with an emphasis on shared resources and cooperation with industry.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116595596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A process design course utilizing micromechanical devices","authors":"M. Lu, M. Schmidt","doi":"10.1109/UGIM.1991.148122","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148122","url":null,"abstract":"Describes a course which is being developed at MIT aimed at incorporation of experimental microfabrication process design at the undergraduate level. They discuss the philosophy and organization of this course and explain how it has been implemented using micromechanical structures as the test vehicle. In particular, a silicon pressure sensor was successfully fabricated by a team of four students in one semester, and was tested and demonstrated to measure pressures in the range of 0-5 psi.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114857617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A fracture mechanics methodology for slow crack growth in thin polyimide films","authors":"V. Kenner, S.F. Popelar, C. Popelar","doi":"10.1109/UGIM.1991.148158","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148158","url":null,"abstract":"A fracture mechanics methodology for assessing the influence of stress and defect size on the structural integrity and life expectancy of thin polyimide films is presented. The approach is a synergistic one that combines fracture mechanics analyses and experiments to quantify slow crack in the films. A viscoelastic fracture model is used to deduce the crack growth history from load-point displacement records measured during long-term fracture tests of the films. The rate of crack growth is found to depend very strongly upon the crack driving force as measured by the stress intensity factor. Hence, small changes in the stress intensity factor can produce dramatic changes in the crack growth rate in the materials investigated.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121492494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automated synthesis of macro/behavioral models for mixed analog/digital circuits, including complete power supply effects","authors":"R. Vogelsong, G. Morency, M. Chian","doi":"10.1109/UGIM.1991.148145","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148145","url":null,"abstract":"The authors describe a system for automated generation of macro/behavioral models for SPICE-based simulation. These tools facilitate the generation of parametric models incorporating fixed and/or variable topologies for a wide range of analog and digital blocks. The macro/behavioral models can operate at several levels of complexity. The highest level models accurately emulate model parametric variation with power supply, transient supply currents, and supply interference effects. Two methodologies are available for defining behavioral models for logic blocks. An even-driven native logic simulator, FLOGIC, has been developed to seamlessly interact with the SPICE engine. FLOGIC provides a systematic and convenient method to create behavioral functions. These functions provide higher accuracy by including second-order effects such as dependencies of propagation delay and thresholds on input signals.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123750260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The establishment of a multi-chip module foundry at RIT","authors":"R. Pearson, P. R. Mukund","doi":"10.1109/UGIM.1991.148157","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148157","url":null,"abstract":"Faculty from the Rochester Institute of Technology's (RIT's) College of Engineering and College of Science have formed a group aimed at advanced multichip module (MCM) packaging of high-speed electronics systems. The authors discuss the cooperation between university, industry, and ultimately the government in an attempt to open up the field of MCM design, fabrication, and use in an educational setting. This group has begun fabrication of both a process evaluation module and actual application-specific modules. The key aspect of the RIT MCM effort is the establishment of an MCM foundry at RIT. The foundry would not be a large-volume foundry, but would provide for internal and supported external MCM fabrication needs. RIT offers a unique fabrication opportunity for MCMs and would like to work with other companies and universities to maximize the exposure of this technology.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124806239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Linking university research to microelectronics manufacturing: Harris Semiconductor's approach to technology transfer","authors":"T. Haycock","doi":"10.1109/UGIM.1991.148110","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148110","url":null,"abstract":"Harris Semiconductor has been successful in its technology transfer programs with universities, and was recently recognized at Semiconductor Research Corporation's (SRC's) TECHCON '90 Conference as having the industry's best mentor program. The author explores methodologies utilized within Harris, with emphasis on its SRC mentor program and summer intern program, each of which targets graduate-level research programs at US universities. The initiation, implementation, and results from both programs are discussed in detail, with emphasis given to manufacturing technology projects. Several case studies explored to illustrate the breadth of applications and technologies that are being addressed.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127775187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}