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2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)最新文献

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Design of a delayless feedback path free 2nd-order two-path time-interleaved discrete-time delta-sigma modulator- a new approach 一种无延迟反馈路径的二阶时间交错离散δ - σ调制器设计新方法
2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA) Pub Date : 2017-05-25 DOI: 10.1109/PRIME-LA.2017.7899174
J. Talebzadeh, I. Kale
{"title":"Design of a delayless feedback path free 2nd-order two-path time-interleaved discrete-time delta-sigma modulator- a new approach","authors":"J. Talebzadeh, I. Kale","doi":"10.1109/PRIME-LA.2017.7899174","DOIUrl":"https://doi.org/10.1109/PRIME-LA.2017.7899174","url":null,"abstract":"This paper presents the design procedure for a 2nd_order two-path Discrete-Time Time-Interleaved (DTTI) ΔΣ modulator from a conventional single-loop 2nd-order Discrete-Time (DT) ΔΣ modulator through the use of time domain equations and time-interleaving concepts [1]. The resulting modulator is free from the delayless feedback path and has only one set of integrators. The delayless feedback path issue in Time-Interleaved (TI) ΔΣ modulators is a critical restriction for the implementation of TI ΔΣ modulators and is effectively eliminated through the use of the approach proposed in this paper. The DTTI ΔΣ modulator requires only three op-amps and two quantizers both of which work concurrently, in comparison to the single-loop DT counterpart that also deploys two op-amps. For an OverSampling Ratio (OSR) of 16 and a clock frequency of 640MHz, our simulation results show a maximum Signal-to-Noise Ratio (SNR) for the DTTI ΔΣ modulator to be 70.5dB with an input bandwidth of 20MHz which has 15dB improvement in comparison to its single-loop, single-path DT counterpart.","PeriodicalId":163037,"journal":{"name":"2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129554122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 280μW sub-threshold Balun LNA for medical radio using current re-use technique 基于电流复用技术的280μW亚阈值Balun LNA
2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA) Pub Date : 2017-02-01 DOI: 10.1109/PRIME-LA.2017.7899171
K. V. Reddy, S. K., P. H
{"title":"A 280μW sub-threshold Balun LNA for medical radio using current re-use technique","authors":"K. V. Reddy, S. K., P. H","doi":"10.1109/PRIME-LA.2017.7899171","DOIUrl":"https://doi.org/10.1109/PRIME-LA.2017.7899171","url":null,"abstract":"A 280 μW current-reuse, sub-threshold balun low noise amplifier (LNA) is presented for medical radio device communication (MedRadio) over the frequency range of 401- 406 MHz. An exemplary balun LNA is designed in a UMC 0.18- μm CMOS technology. The differential conversion of RF input has been procured by stacking power phase splitter (PPS) on top of the inductively degenerated common-source (IDCS) technique. The proposed balun LNA accomplish voltage gain of 19 dB, input & output isolation is less than -14 dB, noise figure of 4.1 dB and IIP3 of -15dBm while consuming 280 μA from 1V supply. The gain & phase error between differential outputs is 1 dB & 0.60 respectively. The layout area of proposed balun LNA core is 0.988mm2.","PeriodicalId":163037,"journal":{"name":"2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115057397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Analysis and comparison of the CV-Dispersion of high-k, bi-layered MOS InGaAs/InP stacks 高k双层MOS InGaAs/InP堆叠的cv -色散分析与比较
2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA) Pub Date : 2017-02-01 DOI: 10.1109/PRIME-LA.2017.7899166
S. Pazos, F. Palumbo, F. Aguirre
{"title":"Analysis and comparison of the CV-Dispersion of high-k, bi-layered MOS InGaAs/InP stacks","authors":"S. Pazos, F. Palumbo, F. Aguirre","doi":"10.1109/PRIME-LA.2017.7899166","DOIUrl":"https://doi.org/10.1109/PRIME-LA.2017.7899166","url":null,"abstract":"In this work, the origin of the C-V dispersion in accumulation on High-k Bi-layered InGaAs and InP substrate MOS capacitors is discussed. Using different proportions of Al2O3 and HfO2 dielectrics on a 10nm thick gate insulator, the influence of each layer and its defects is studied. Results show that increasing the thickness of the Al2O3 interfacial layer contributes to improve the quality of the structure in terms of border trap density. InP based stacks show the same tendencies of InGaAs based stacks, but with a higher overall dispersion attributed to the quality of the dielectric deposition on different substrates.","PeriodicalId":163037,"journal":{"name":"2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)","volume":"515 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116212245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Experimental study of progressive breakdown in different conductance states of resistive switching structures 电阻开关结构不同电导状态下递进击穿的实验研究
2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA) Pub Date : 2017-02-01 DOI: 10.1109/PRIME-LA.2017.7899167
F. Aguirre, S. Pazos, F. Palumbo
{"title":"Experimental study of progressive breakdown in different conductance states of resistive switching structures","authors":"F. Aguirre, S. Pazos, F. Palumbo","doi":"10.1109/PRIME-LA.2017.7899167","DOIUrl":"https://doi.org/10.1109/PRIME-LA.2017.7899167","url":null,"abstract":"In this work, the breakdown transients of Al2O3- and HfO2-based metal-insulator-metal (MIM) stacks with the same oxide thickness and identical metal electrodes are studied. The differences and similarities between these transients in the progressive breakdown regime are assessed. Results show that Al2O3 exhibits longer breakdown transients than HfO2 and requires a higher voltage to initiate a very fast current runaway across the dielectric film. Similar results are observed when the devices are in remarkably different conductive states reached as a consequence of a resistive switching event. This suggests that both resistive switching and breakdown processes are linked to the thermal properties of the oxides under test rather than to dissipation effects occurring at the metal electrodes.","PeriodicalId":163037,"journal":{"name":"2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127118629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Programmable assertion checkers for hardware Trojan detection 可编程的断言检查硬件木马检测
2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA) Pub Date : 2017-02-01 DOI: 10.1109/PRIME-LA.2017.7899173
Uthman Alsaiari, F. Gebali, M. Abd-El-Barr
{"title":"Programmable assertion checkers for hardware Trojan detection","authors":"Uthman Alsaiari, F. Gebali, M. Abd-El-Barr","doi":"10.1109/PRIME-LA.2017.7899173","DOIUrl":"https://doi.org/10.1109/PRIME-LA.2017.7899173","url":null,"abstract":"Due to the increase in design complexity and cost of VLSI chips, a number of design houses outsource manufacturing and import designs in a way to reduce the cost. This results in a decrease of the authenticity and security of the manufactured product. Since product development involves outside sources, circuit designers can not guarantee that their hardware has not been altered. It is often possible that attackers include additional hardware in order to gain privileges over the original circuit or cause damage to the product. These added circuits are called “Hardware Trojans”. In this paper, we investigate introducing necessary modules needed for detection of hardware Trojans. We also introduce necessary programmable logic fabric that can be used in the implementation of the hardware assertion checkers. Our target is to utilize the provided programable fabric in a System on Chip (SoC) and optimize the hardware assertion to cover the detection of most hardware trojans in each core of the target SoC.","PeriodicalId":163037,"journal":{"name":"2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127046128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Grid-voltage sensorless control of an LCL filter with low resonance frequency 低谐振频率LCL滤波器的无电网电压传感器控制
2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA) Pub Date : 2017-02-01 DOI: 10.1109/PRIME-LA.2017.7899175
R. Fantino, C. Busada, J. Solsona
{"title":"Grid-voltage sensorless control of an LCL filter with low resonance frequency","authors":"R. Fantino, C. Busada, J. Solsona","doi":"10.1109/PRIME-LA.2017.7899175","DOIUrl":"https://doi.org/10.1109/PRIME-LA.2017.7899175","url":null,"abstract":"A Grid-Voltage sensorless control strategy for LCL Grid-connected voltage source inverters is proposed. Positive and negative grid sequences used for synchronization are estimated using an observer. The control of the system is implemented with a strategy that allows the use of the proportional plus resonant regulator (PR) optimum design, regardless of the filter resonance frequency. The effectiveness of the proposal is demonstrated by simulation in a realistic scenario.","PeriodicalId":163037,"journal":{"name":"2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123132687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
AES block cipher implementations with AMBA-AHB interface AES分组密码实现与AMBA-AHB接口
2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA) Pub Date : 2017-02-01 DOI: 10.1109/PRIME-LA.2017.7899170
Paola Ceminari, Ariel Arelovich, M. D. Federico
{"title":"AES block cipher implementations with AMBA-AHB interface","authors":"Paola Ceminari, Ariel Arelovich, M. D. Federico","doi":"10.1109/PRIME-LA.2017.7899170","DOIUrl":"https://doi.org/10.1109/PRIME-LA.2017.7899170","url":null,"abstract":"The aim of this work is to describe three different architectural designs for AES cipher, which is a symmetric block encryption standard. The three architectures are oriented to different applications and are designed using different approaches, like pipeline structures and resource sharing. They also include an AMBA AHB interface, which is an open standard that defines the interconnection of blocks in a System-on-Chip (SoC).","PeriodicalId":163037,"journal":{"name":"2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117087513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
HDL and design techniques analysis for FPGA & ASIC synthesis FPGA与ASIC合成的HDL与设计技术分析
2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA) Pub Date : 2017-02-01 DOI: 10.1109/PRIME-LA.2017.7899168
Paola Ceminari, Ariel Oroz De Gaetano, Jorge Bellini, M. D. Federico
{"title":"HDL and design techniques analysis for FPGA & ASIC synthesis","authors":"Paola Ceminari, Ariel Oroz De Gaetano, Jorge Bellini, M. D. Federico","doi":"10.1109/PRIME-LA.2017.7899168","DOIUrl":"https://doi.org/10.1109/PRIME-LA.2017.7899168","url":null,"abstract":"This work presents the design of a Morse decoder implemented using fourteen different architectures described in Verilog. All designs are synthesized in FPGA and ASIC, using Xilinx ISE and Vivado for the former and Leonardo Spectrum and Design Compiler for the latter. The performance and resource requirements after synthesis of each architecture are compared to gain insight on the impact caused by using different design styles, description techniques, architectural variants and the circuit’s final target.","PeriodicalId":163037,"journal":{"name":"2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116536556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Synthesis and design of a 4th order low-pass DT sigma-delta modulator in a 130nm cmos process 四阶低通DT σ - δ调制器的合成与设计
2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA) Pub Date : 2017-02-01 DOI: 10.1109/PRIME-LA.2017.7899177
D. Calderón-Preciado, F. Sandoval-Ibarra, F. Silveira
{"title":"Synthesis and design of a 4th order low-pass DT sigma-delta modulator in a 130nm cmos process","authors":"D. Calderón-Preciado, F. Sandoval-Ibarra, F. Silveira","doi":"10.1109/PRIME-LA.2017.7899177","DOIUrl":"https://doi.org/10.1109/PRIME-LA.2017.7899177","url":null,"abstract":"This paper summarizes the research work carried out during a doctorate studies, which is focused on the synthesis and design of a 4th Order ΣΔ Modulator in Discrete Time (DT) implemented in a 130nm CMOS process. By means of SIMSIDES the high-level simulation of the modulator is analyzed in order to translate the design specifications into a set of values such that the transistor level blocks be established by the desired performance of the proposed architecture. At the transistor level design, special attention is focused to the OTA, since this block is the main source of non-idealities in a Switched Capacitor (SC) Integrator. Moreover, the gm/ID methodology is implemented into this stage as a tool to obtain the optimum circuit performance based on power consumption and better signal-to-noise ratio.","PeriodicalId":163037,"journal":{"name":"2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127062674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Robustness evaluation of finFET transistors under PVT variability PVT变异性下finFET晶体管鲁棒性评价
2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA) Pub Date : 2017-02-01 DOI: 10.1109/PRIME-LA.2017.7899176
A. Zimpeck, C. Meinhardt, R. Reis
{"title":"Robustness evaluation of finFET transistors under PVT variability","authors":"A. Zimpeck, C. Meinhardt, R. Reis","doi":"10.1109/PRIME-LA.2017.7899176","DOIUrl":"https://doi.org/10.1109/PRIME-LA.2017.7899176","url":null,"abstract":"This work provides a predictive evaluation of the impact that PVT variability causes on ON and OFF currents of FinFET transistors in technologies sub-22nm. Results show that the OFF current is the most impacted by all sources of variability. In terms of process variability effects, the LG and WFF variations cause the worst values to IOFF, especially for PFET and NFET devices, respectively. Voltage and temperature variations effects damage more the PFET devices.","PeriodicalId":163037,"journal":{"name":"2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128238230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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