Synthesis and design of a 4th order low-pass DT sigma-delta modulator in a 130nm cmos process

This paper summarizes the research work carried out during a doctorate studies, which is focused on the synthesis and design of a 4th Order ΣΔ Modulator in Discrete Time (DT) implemented in a 130nm CMOS process. By means of SIMSIDES the high-level simulation of the modulator is analyzed in order to translate the design specifications into a set of values such that the transistor level blocks be established by the desired performance of the proposed architecture. At the transistor level design, special attention is focused to the OTA, since this block is the main source of non-idealities in a Switched Capacitor (SC) Integrator. Moreover, the gm/ID methodology is implemented into this stage as a tool to obtain the optimum circuit performance based on power consumption and better signal-to-noise ratio.