一种无延迟反馈路径的二阶时间交错离散δ - σ调制器设计新方法

J. Talebzadeh, I. Kale
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引用次数: 0

摘要

本文通过使用时域方程和时间交错概念[1],介绍了从传统的单回路二阶离散时间(DT) ΔΣ调制器到二阶双路径离散时间交错(DTTI) ΔΣ调制器的设计过程。所得到的调制器不受无延迟反馈路径的影响,并且只有一组积分器。时间交错(TI) ΔΣ调制器中的无延迟反馈路径问题是实现TI ΔΣ调制器的一个关键限制,通过使用本文提出的方法可以有效地消除。DTTI ΔΣ调制器只需要三个运算放大器和两个量化器同时工作,而单回路DT调制器也需要部署两个运算放大器。在过采样比(OSR)为16、时钟频率为640MHz的情况下,我们的仿真结果显示,DTTI ΔΣ调制器在输入带宽为20MHz时的最大信噪比(SNR)为70.5dB,与单环单路DT调制器相比,提高了15dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of a delayless feedback path free 2nd-order two-path time-interleaved discrete-time delta-sigma modulator- a new approach
This paper presents the design procedure for a 2nd_order two-path Discrete-Time Time-Interleaved (DTTI) ΔΣ modulator from a conventional single-loop 2nd-order Discrete-Time (DT) ΔΣ modulator through the use of time domain equations and time-interleaving concepts [1]. The resulting modulator is free from the delayless feedback path and has only one set of integrators. The delayless feedback path issue in Time-Interleaved (TI) ΔΣ modulators is a critical restriction for the implementation of TI ΔΣ modulators and is effectively eliminated through the use of the approach proposed in this paper. The DTTI ΔΣ modulator requires only three op-amps and two quantizers both of which work concurrently, in comparison to the single-loop DT counterpart that also deploys two op-amps. For an OverSampling Ratio (OSR) of 16 and a clock frequency of 640MHz, our simulation results show a maximum Signal-to-Noise Ratio (SNR) for the DTTI ΔΣ modulator to be 70.5dB with an input bandwidth of 20MHz which has 15dB improvement in comparison to its single-loop, single-path DT counterpart.
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