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2017 Iranian Conference on Electrical Engineering (ICEE)最新文献

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Distribution Locational Marginal Price analysis considering technical constraints 考虑技术约束的配送区位边际价格分析
2017 Iranian Conference on Electrical Engineering (ICEE) Pub Date : 2017-05-02 DOI: 10.1109/IRANIANCEE.2017.7985189
Saeed Nematshahi, H. R. Mashhadi
{"title":"Distribution Locational Marginal Price analysis considering technical constraints","authors":"Saeed Nematshahi, H. R. Mashhadi","doi":"10.1109/IRANIANCEE.2017.7985189","DOIUrl":"https://doi.org/10.1109/IRANIANCEE.2017.7985189","url":null,"abstract":"According to the increasing penetration rate of microgrids, as responsive loads in the distribution system, it's important to consider this potential as an active player in the electricity market. Distribution system, with its characteristic features such as radial topology, low voltage level and high ratio of resistance to inductance of lines, possess exclusive specifications. This paper presents a comprehensive study to determine importance of Locational Marginal Price (LMP) in distribution level, known as Distribution Locational Marginal Price (DLMP). Application of DLMP authorize the Distribution System Operator (DSO) to make optimal decisions in network operation as well as network planning. The standard IEEE 33-bus network has been chosen as a suitable case study, where the impact of some technical constraints on DLMP have been numerically analyzed. The obtained results indicate significant change in the market clearing price. In particular, voltage constraint and line flow limitation investigate in the presence of microgrids as a responsive load. In addition, the effect of transformer tap changer and capacitor bank, as a traditional approach in voltage control of distribution systems, has been addressed.","PeriodicalId":161929,"journal":{"name":"2017 Iranian Conference on Electrical Engineering (ICEE)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131431974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Development of stochastic optimal controller for Itô uncertain model of active suspension system 主动悬架系统Itô不确定模型随机最优控制器的研制
2017 Iranian Conference on Electrical Engineering (ICEE) Pub Date : 2017-05-02 DOI: 10.1109/IRANIANCEE.2017.7985108
Alireza Ramezani Moghadam, H. Kebriaei
{"title":"Development of stochastic optimal controller for Itô uncertain model of active suspension system","authors":"Alireza Ramezani Moghadam, H. Kebriaei","doi":"10.1109/IRANIANCEE.2017.7985108","DOIUrl":"https://doi.org/10.1109/IRANIANCEE.2017.7985108","url":null,"abstract":"In this paper, Itô-type stochastic optimal control approach for uncertain model of vehicle suspension is developed. The model of quarter-car is constructed using linear characteristics of damping and springs. In order to elicit Itô stochastic dynamic of vehicle, parametric perturbations of sprung damping and spring characteristics are taken into account. Furthermore, the road disturbance is considered as a Gaussian white noise process. By using stochastic Hamilton-Jacobi-Bellman method, the stochastic optimal linear quadratic regulator controller for active suspension system is designed. Based on the concept of stochastic stability and using extension of Lyapunov method for Itô uncertain models, it is proven that the optimal control law, stochastically stabilizes the active perturbed suspension system. Moreover, it is shown that the well-known linear quadratic Gaussian controller cannot stabilize the perturbed system in certain conditions given by a linear matrix inequality. A simulation study is performed to evaluate the effectiveness of proposed stochastic control approach.","PeriodicalId":161929,"journal":{"name":"2017 Iranian Conference on Electrical Engineering (ICEE)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121531557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Interaction between DNA-nucleotides and nanopores in h-BN/graphene devices: An ab initio study h-BN/石墨烯器件中dna核苷酸与纳米孔之间的相互作用:从头开始研究
2017 Iranian Conference on Electrical Engineering (ICEE) Pub Date : 2017-05-02 DOI: 10.1109/IRANIANCEE.2017.7985088
Amir Safarpoor Kordbacheh, Ali Kia, E. Nadimi
{"title":"Interaction between DNA-nucleotides and nanopores in h-BN/graphene devices: An ab initio study","authors":"Amir Safarpoor Kordbacheh, Ali Kia, E. Nadimi","doi":"10.1109/IRANIANCEE.2017.7985088","DOIUrl":"https://doi.org/10.1109/IRANIANCEE.2017.7985088","url":null,"abstract":"Fundamental electronic properties of nanopore-based DNA sequencing device have been investigated applying density functional theory. A device consisting of a nanopore in a h-BN layer, which is sandwiched between two graphene electrodes has been proposed. Properties such as absorption energy, density of states and charge transfer between four DNA nucleotides and device have been calculated considering two different alignments of nucleotides in nanopore. The significance of rotation for these DNA nucleotides has been discussed through the results.","PeriodicalId":161929,"journal":{"name":"2017 Iranian Conference on Electrical Engineering (ICEE)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114357792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High resolution CMOS voltage comparator for high speed SAR ADCs 用于高速SAR adc的高分辨率CMOS电压比较器
2017 Iranian Conference on Electrical Engineering (ICEE) Pub Date : 2017-05-02 DOI: 10.1109/IRANIANCEE.2017.7985091
Nader Sharifi Gharabaghlo, T. M. Khaneshan
{"title":"High resolution CMOS voltage comparator for high speed SAR ADCs","authors":"Nader Sharifi Gharabaghlo, T. M. Khaneshan","doi":"10.1109/IRANIANCEE.2017.7985091","DOIUrl":"https://doi.org/10.1109/IRANIANCEE.2017.7985091","url":null,"abstract":"By means of a standard 0.18µm CMOS process a novel CMOS voltage comparator circuit has been proposed which is capable of resolving 400µV. Employing preamplifier latch structure the designed circuit operates at the clock frequency of 100MHz. The main advantage of the implemented comparator is its 11 bit resolution which makes it a good choice for high resolution SAR ADCs. In order to reduce the power consumption some modifications are made to the conventional structure of the comparator which resulted in reduction of employed transistors as well as active area on chip. Post-layout simulation results confirm the correct behavior of the proposed architecture while the power dissipation is 900µW from a 1.8V power supply.","PeriodicalId":161929,"journal":{"name":"2017 Iranian Conference on Electrical Engineering (ICEE)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116076556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A new high speed phase detection circuit with π phase difference detection 一种具有π相位差检测的高速相位检测电路
2017 Iranian Conference on Electrical Engineering (ICEE) Pub Date : 2017-05-02 DOI: 10.1109/IRANIANCEE.2017.7985474
Saeed Taheri, Noushin Ghaderi, Amin Amani
{"title":"A new high speed phase detection circuit with π phase difference detection","authors":"Saeed Taheri, Noushin Ghaderi, Amin Amani","doi":"10.1109/IRANIANCEE.2017.7985474","DOIUrl":"https://doi.org/10.1109/IRANIANCEE.2017.7985474","url":null,"abstract":"This paper proposed a new structure of Dynamic-Logic Phase Detector (PD) and a π detection circuit. A very simple, low power consumption, high maximum operating frequency and high precision PD is presented. In addition the proposed circuit is based on an open loop architecture and solves the blind-zone and dead zone problems of the conventional circuits. Most PDs have a main problem when the phase difference of two inputs is 180°. In this situation, the loop becomes locked in wrong mode. To solve this problem, a π detection circuit is proposed which, generates an error signal to prevent from locking at π phase difference. SPICE simulation results show that, operational frequency range of proposed PD is 1MHz to 8GHz. The circuit has been designed in 0.18µm CMOS technology. The power consumption of circuit is 0.6 mW at highest frequency.","PeriodicalId":161929,"journal":{"name":"2017 Iranian Conference on Electrical Engineering (ICEE)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132767404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A new Fractional-N frequency synthesizer using Nested-PLL architecture 采用嵌套锁相环结构的新型分数n频率合成器
2017 Iranian Conference on Electrical Engineering (ICEE) Pub Date : 2017-05-02 DOI: 10.1109/IRANIANCEE.2017.7985408
Mohammadreza Jamali, Emad Ebrahimi
{"title":"A new Fractional-N frequency synthesizer using Nested-PLL architecture","authors":"Mohammadreza Jamali, Emad Ebrahimi","doi":"10.1109/IRANIANCEE.2017.7985408","DOIUrl":"https://doi.org/10.1109/IRANIANCEE.2017.7985408","url":null,"abstract":"Delta-sigma modulators (DSM) in conventional Fractional-N PLLs produce quantization noise and can't remove fractional spurs around the main frequency well. In order to reduce the spurs in Fractional-N synthesizers, a new Nested-PLL has been presented in this work. The proposed Fractional-N PLL consists of a conventional PLL as a frequency multiplier (*M) in feedback path that make fraction M/N along divider (N). In the other words the fraction M/N is achieved by a Nested-PLL instead of delta-sigma modulator. Therefore, spurs caused by delta-sigma modulator or pulse swallower is removed. The proposed Nested-PLL and its stability issues are addressed in this paper. Also to verify the proposed structure a prototype of the synthesizer with Fref=100MHz and Fout=1GHz–1.3GHz designed and simulated systematically, and no fractional spurs are observed.","PeriodicalId":161929,"journal":{"name":"2017 Iranian Conference on Electrical Engineering (ICEE)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123463036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel high speed CMOS pseudo-differential ring VCO with wide tuning control voltage range 一种新型高速宽调谐控制电压范围的CMOS伪差分环压控振荡器
2017 Iranian Conference on Electrical Engineering (ICEE) Pub Date : 2017-05-02 DOI: 10.1109/IRANIANCEE.2017.7985438
Saman Kamran, Noushin Ghaderi
{"title":"A novel high speed CMOS pseudo-differential ring VCO with wide tuning control voltage range","authors":"Saman Kamran, Noushin Ghaderi","doi":"10.1109/IRANIANCEE.2017.7985438","DOIUrl":"https://doi.org/10.1109/IRANIANCEE.2017.7985438","url":null,"abstract":"In this paper a novel three-stage pseudo-differential ring voltage controlled oscillator (VCO) based on Park-Kim ring VCO with high speed and a wide tuning control voltage range is proposed. By using the inductive shunt peaking technique with Hara active inductors a wide bandwidth is obtained. A pair of PMOS transistors with gates connected to the controlled-voltage is added to increase the oscillation frequency and tuning control voltage range. The phase noise is also reduced by minimizing signal transition period in which noise current has critical impact on the phase noise. The circuit is simulated in 0.18 µm CMOS technology with supply voltage of 1.8V and power consumption of 8.3mW. A VCO with wide tuning frequency range from 3.1 GHz to 10.1 GHz is achieved by using this technique. The measured phase noise of this ring VCO are −113 dBc/Hz at a 1-MHz offset.","PeriodicalId":161929,"journal":{"name":"2017 Iranian Conference on Electrical Engineering (ICEE)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125104145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
0.4 V ultra-low voltage differential CMOS Schmitt trigger 0.4 V超低压差分CMOS施密特触发器
2017 Iranian Conference on Electrical Engineering (ICEE) Pub Date : 2017-05-02 DOI: 10.1109/IRANIANCEE.2017.7985096
A. Nejati, Yasin Bastan, P. Amiri
{"title":"0.4 V ultra-low voltage differential CMOS Schmitt trigger","authors":"A. Nejati, Yasin Bastan, P. Amiri","doi":"10.1109/IRANIANCEE.2017.7985096","DOIUrl":"https://doi.org/10.1109/IRANIANCEE.2017.7985096","url":null,"abstract":"In this paper, we present an ultra-low voltage differential CMOS Schmitt trigger. Bulk-driven and sub-threshold techniques are used to achieve low voltage operation in the proposed circuit. The regenerative current feedback is also used to generation the hysteresis of the opamp-based Schmitt trigger in this paper. The proposed Schmitt trigger is designed and simulated in 0.18µm CMOS technology and it is operated in 0.4 V supply voltage.","PeriodicalId":161929,"journal":{"name":"2017 Iranian Conference on Electrical Engineering (ICEE)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116749206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Face recognition using morphological profile and feature space discriminant analysis 基于形态轮廓和特征空间判别分析的人脸识别
2017 Iranian Conference on Electrical Engineering (ICEE) Pub Date : 2017-05-02 DOI: 10.1109/IRANIANCEE.2017.7985329
M. Imani, G. Montazer
{"title":"Face recognition using morphological profile and feature space discriminant analysis","authors":"M. Imani, G. Montazer","doi":"10.1109/IRANIANCEE.2017.7985329","DOIUrl":"https://doi.org/10.1109/IRANIANCEE.2017.7985329","url":null,"abstract":"Two face recognition methods based on morphological filters and feature space discriminant analysis (FSDA) are proposed in this paper. Both the proposed methods calculate the morphological profile (MP) of each face sample. The MP contains the contextual information of the face image. Moreover, FSDA, which is a novel feature extraction method introduced in 2015, extracts features with minimum redundant information and maximum class discrimination one. The first proposed method just uses the first component of MP obtained by FSDA, while the second proposed method uses the whole images provided by all opening and closing filters by reconstruction. The dimensionality of each filtered image is reduced by FSDA. Then, the features are fed to a nearest neighbor classifier. Finally the decision fusion rule is used to find the label of each test face image. The experimental results on ORL and Yale face databases show the superior performance of the proposed methods compared to some popular and state-of-the-art face recognition methods.","PeriodicalId":161929,"journal":{"name":"2017 Iranian Conference on Electrical Engineering (ICEE)","volume":"212 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113991118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Electric vehicles connection to microgrid effects on peak demand with and without demand response 电动汽车接入微电网对峰值需求的影响
2017 Iranian Conference on Electrical Engineering (ICEE) Pub Date : 2017-05-02 DOI: 10.1109/IRANIANCEE.2017.7985237
Sahand Liasi, M. Golkar
{"title":"Electric vehicles connection to microgrid effects on peak demand with and without demand response","authors":"Sahand Liasi, M. Golkar","doi":"10.1109/IRANIANCEE.2017.7985237","DOIUrl":"https://doi.org/10.1109/IRANIANCEE.2017.7985237","url":null,"abstract":"Electric vehicles (EVs) are early future transportation facilities, so it is important to study their impacts on grids. In this paper, EVs impact on peak demand is investigated by stochastic approach and its effects is studied both with and without considering the demand response. In addition, the same study has been performed for linear and nonlinear charge characteristics effects. Results show notable peak demand increment while connecting EVs without demand response consideration, in addition, demand response activities by vehicle to grid connection have a great impact on peak shaving.","PeriodicalId":161929,"journal":{"name":"2017 Iranian Conference on Electrical Engineering (ICEE)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132747915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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