A new Fractional-N frequency synthesizer using Nested-PLL architecture

Abstract

Delta-sigma modulators (DSM) in conventional Fractional-N PLLs produce quantization noise and can't remove fractional spurs around the main frequency well. In order to reduce the spurs in Fractional-N synthesizers, a new Nested-PLL has been presented in this work. The proposed Fractional-N PLL consists of a conventional PLL as a frequency multiplier (*M) in feedback path that make fraction M/N along divider (N). In the other words the fraction M/N is achieved by a Nested-PLL instead of delta-sigma modulator. Therefore, spurs caused by delta-sigma modulator or pulse swallower is removed. The proposed Nested-PLL and its stability issues are addressed in this paper. Also to verify the proposed structure a prototype of the synthesizer with Fref=100MHz and Fout=1GHz–1.3GHz designed and simulated systematically, and no fractional spurs are observed.