{"title":"采用嵌套锁相环结构的新型分数n频率合成器","authors":"Mohammadreza Jamali, Emad Ebrahimi","doi":"10.1109/IRANIANCEE.2017.7985408","DOIUrl":null,"url":null,"abstract":"Delta-sigma modulators (DSM) in conventional Fractional-N PLLs produce quantization noise and can't remove fractional spurs around the main frequency well. In order to reduce the spurs in Fractional-N synthesizers, a new Nested-PLL has been presented in this work. The proposed Fractional-N PLL consists of a conventional PLL as a frequency multiplier (*M) in feedback path that make fraction M/N along divider (N). In the other words the fraction M/N is achieved by a Nested-PLL instead of delta-sigma modulator. Therefore, spurs caused by delta-sigma modulator or pulse swallower is removed. The proposed Nested-PLL and its stability issues are addressed in this paper. Also to verify the proposed structure a prototype of the synthesizer with Fref=100MHz and Fout=1GHz–1.3GHz designed and simulated systematically, and no fractional spurs are observed.","PeriodicalId":161929,"journal":{"name":"2017 Iranian Conference on Electrical Engineering (ICEE)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A new Fractional-N frequency synthesizer using Nested-PLL architecture\",\"authors\":\"Mohammadreza Jamali, Emad Ebrahimi\",\"doi\":\"10.1109/IRANIANCEE.2017.7985408\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Delta-sigma modulators (DSM) in conventional Fractional-N PLLs produce quantization noise and can't remove fractional spurs around the main frequency well. In order to reduce the spurs in Fractional-N synthesizers, a new Nested-PLL has been presented in this work. The proposed Fractional-N PLL consists of a conventional PLL as a frequency multiplier (*M) in feedback path that make fraction M/N along divider (N). In the other words the fraction M/N is achieved by a Nested-PLL instead of delta-sigma modulator. Therefore, spurs caused by delta-sigma modulator or pulse swallower is removed. The proposed Nested-PLL and its stability issues are addressed in this paper. Also to verify the proposed structure a prototype of the synthesizer with Fref=100MHz and Fout=1GHz–1.3GHz designed and simulated systematically, and no fractional spurs are observed.\",\"PeriodicalId\":161929,\"journal\":{\"name\":\"2017 Iranian Conference on Electrical Engineering (ICEE)\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-05-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Iranian Conference on Electrical Engineering (ICEE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IRANIANCEE.2017.7985408\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Iranian Conference on Electrical Engineering (ICEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRANIANCEE.2017.7985408","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new Fractional-N frequency synthesizer using Nested-PLL architecture
Delta-sigma modulators (DSM) in conventional Fractional-N PLLs produce quantization noise and can't remove fractional spurs around the main frequency well. In order to reduce the spurs in Fractional-N synthesizers, a new Nested-PLL has been presented in this work. The proposed Fractional-N PLL consists of a conventional PLL as a frequency multiplier (*M) in feedback path that make fraction M/N along divider (N). In the other words the fraction M/N is achieved by a Nested-PLL instead of delta-sigma modulator. Therefore, spurs caused by delta-sigma modulator or pulse swallower is removed. The proposed Nested-PLL and its stability issues are addressed in this paper. Also to verify the proposed structure a prototype of the synthesizer with Fref=100MHz and Fout=1GHz–1.3GHz designed and simulated systematically, and no fractional spurs are observed.