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2019 X Southern Conference on Programmable Logic (SPL)最新文献

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An Application of the Hardened Floating-Point Cores on HIL Simulations 强化浮点核在HIL仿真中的应用
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-10 DOI: 10.1109/SPL.2019.8714315
E. Todorovich, Alberto Sánchez, Á. de Castro
{"title":"An Application of the Hardened Floating-Point Cores on HIL Simulations","authors":"E. Todorovich, Alberto Sánchez, Á. de Castro","doi":"10.1109/SPL.2019.8714315","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714315","url":null,"abstract":"Programmable logic is becoming usual in Hardware-In-the-Loop (HIL) emulation due to its acceleration capabilities. HIL technique is specifically useful for verifying power electronics. But even using programmable logic, if integration steps below 100 ns are required and floating-point is the chosen representation, it has not been possible to reach real time simulations. With the release of devices with HFP (Hardened Floating-Point) cores -dedicated floating-point blocks implemented in silicon-, the minimum achievable simulation step decreases significantly. This work shows an implementation of a full-bridge converter model using HFP cores. Results show that the HFP-based model achieve a simulation step around 10 ns in this case. However, when decreasing the integration step, numerical resolution can become an issue. Thus, designers face a trade-off before selecting 32-bit floating-point representation for a model: better integration steps vs. accuracy limits. In this way, resolution and accuracy are also studied.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126163529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pipelining on FPGAs: A Tutorial fpga上的流水线:教程
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-10 DOI: 10.1109/SPL.2019.8714285
E. Boemo
{"title":"Pipelining on FPGAs: A Tutorial","authors":"E. Boemo","doi":"10.1109/SPL.2019.8714285","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714285","url":null,"abstract":"This tutorial reviews historical milestones and main concepts regarding the pipelining of electronic circuits. Although the technique emerged in the 1960s, it remains a direct way to simultaneously increase throughput and reduce power in FPGA-based systems. However, the efficacy of pipelining is limited by the dominance of register and routing delays. This work focuses on bit-level pipelining. It analyses by examples keys aspects such as construction hints, pipeline metrics, effects of registering, preferential pipeline directions, and synchronization failures. The text condenses the first section of the invited tutorial lecture at the 2019 Southern Conference on Programmable Logic (SPL). Whenever is possible, numeric examples are particularized to FPGA technology, but in some cases, cell-based ASICs data are deemed more convenient. The ideas would be useful for students of an advanced course on digital electronics, or PhD candidates interested in the details of the design of integrated circuits.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130095641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design for Portability of Reconfigurable Virtual Instrumentation 可重构虚拟仪器的可移植性设计
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-10 DOI: 10.1109/SPL.2019.8714446
K. Mannatunga, Luis G.G. Ordóñez, Marie B. Amador, M. Crespo, A. Cicuttin, S. Levorato, R. Melo, B. Valinoti
{"title":"Design for Portability of Reconfigurable Virtual Instrumentation","authors":"K. Mannatunga, Luis G.G. Ordóñez, Marie B. Amador, M. Crespo, A. Cicuttin, S. Levorato, R. Melo, B. Valinoti","doi":"10.1109/SPL.2019.8714446","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714446","url":null,"abstract":"A portable architectural design strategy is described for the implementation of reconfigurable virtual instrumentation based on programmable Systems-on-Chip integrating microprocessors and FPGA in the same physical device. The key role is played by a general purpose communication block as a means to efficiently separate the activities carried out in the microprocessor and in the FPGA. Both parts interact according to simple logic protocols by reading and writing data on the common memory resources of the communication block. The architecture of the proposed communication system can be easily implemented in practically any modern programmable System-on-Chip. With the proposed strategy, the porting of embedded software programs and associated FPGA designs among different device families and vendors is facilitated. A structured methodology is proposed for handling complex real-time systems based on these programmable Systems-on-Chip. We described a concrete communication block that has been successfully implemented and utilized for a quick implementation of a data acquisition system based on a Xilinx Zynq-7030 FPGA Mezzanine Card (FMC) and a custom FMC module with an 8-bit 500 MSPS ADC.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123801878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Study of the Data Exchange Between Programmable Logic and Processor System of Zynq-7000 Devices Zynq-7000器件可编程逻辑与处理器系统数据交换的研究
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-10 DOI: 10.1109/SPL.2019.8714328
R. Melo, B. Valinoti, Marie Baly Amador, Luis G. García, A. Cicuttin, María Liz Crespo
{"title":"Study of the Data Exchange Between Programmable Logic and Processor System of Zynq-7000 Devices","authors":"R. Melo, B. Valinoti, Marie Baly Amador, Luis G. García, A. Cicuttin, María Liz Crespo","doi":"10.1109/SPL.2019.8714328","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714328","url":null,"abstract":"Zynq-7000 devices from Xilinx has gained strong popularity in the last years. Several documents and examples about interfaces usage and how to communicate the programmable logic with the processor are available, but some of them are not properly explained and in particular, the maximum throughput is not clearly specified. With this purpose, in this work a measurement method is presented and applied over the five available interfaces, considering the most used alternatives. Tests were carried on a Zybo board, but the results can be easily used to estimate the performance of others systems setups. Special hardware features and functionality are also discussed, providing a better understanding of system performance. Related papers were studied but none of them presents comparable information as to provide a fair comparison.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129294108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Low Power FPGA Based Control Unit for an Implantatable Neuromodulation Circuit 植入式神经调节电路的低功耗FPGA控制单元
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/SPL.2019.8714506
Santiago Martínez, J. Oliver
{"title":"A Low Power FPGA Based Control Unit for an Implantatable Neuromodulation Circuit","authors":"Santiago Martínez, J. Oliver","doi":"10.1109/SPL.2019.8714506","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714506","url":null,"abstract":"This paper presents the design of a FPGA based control unit for an implantable neuromodulation circuit. The design was validated at both logical and functional level and it was implemented in three different FPGA, from different families and manufacturers: 5CEBA4 (CycloneV family) by Intel, M2GL025 (IGL002 family) by Microsemi and HX-8K (iCE40 family) by Lattice. The design uses several parameterized constants such as output electrode number, therapy number and system clock frequency to create different sort of instances at synthesis time. For a given configuration with 4 therapies and 16 electrodes the design required less than 3900 logic elements. For that configuration the FPGAs total core power consumption was measured at 37°C and 7.8 MHz. The results were as low as 3.6 mW when delivering a continuous stimulation burst at a frequency of 10 kHz.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"65 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134005356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Digital Count-Rate Meter and Flux-Change-Rate Meter with Automatic Adjust of Counting Time Based on FPGA for Pulse-Mode Flux Measurements in Nuclear Reactors 基于FPGA的数字计数速率计和计数时间自动调节的通量变化率计用于核反应堆脉冲模式通量测量
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/SPL.2019.8714262
Gloria Ríos, D. Estryk, C. Verrastro
{"title":"Digital Count-Rate Meter and Flux-Change-Rate Meter with Automatic Adjust of Counting Time Based on FPGA for Pulse-Mode Flux Measurements in Nuclear Reactors","authors":"Gloria Ríos, D. Estryk, C. Verrastro","doi":"10.1109/SPL.2019.8714262","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714262","url":null,"abstract":"This paper describes a digital count-rate meter and flux-change-rate meter implemented using Field Programmable Gate Array (FPGA) technology with proprietary algorithms developed for measuring pulse-mode flux and its variations at startup of nuclear research reactors. Due to its auto-adjusting counting time implementation which optimizes the trade-off between statistical precision and response time, it provides a wide range of count-rate from 0.1 to $pmb{10^{6}}$ pulse per second with response time inversely proportional to the actual count-rate.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116368169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Towards 100 GbE FPGA-Based Flow Monitoring 迈向100gbe fpga流量监控
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/SPL.2019.8714532
T. Alonso, Mario Ruiz, G. Sutter, Sergio López-Buedo, Jorge E. López De Vergara
{"title":"Towards 100 GbE FPGA-Based Flow Monitoring","authors":"T. Alonso, Mario Ruiz, G. Sutter, Sergio López-Buedo, Jorge E. López De Vergara","doi":"10.1109/SPL.2019.8714532","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714532","url":null,"abstract":"This paper explores the problem of flow metering in 100 GbE links, presenting a flow exporter architecture based on a FPGA acceleration card using only on-chip memory. Peak performance without packet sampling even at the maximum packet rate is assured and means to avoid data loss are provided, since a low level of aggregation is achieved. This is the first approach in a series of architectures that are built upon the previous one, where the resources of the custom hardware are gradually increased, improving the aggregation level, while the required commodity hardware resources for subsequent stages are consequently lowered. We consider that FPGA-fabric offers adequate flexibility and performance for this task and is capable of reducing overall system cost. A functional prototype of the system has been implemented on the Xilinx VCU118 development board configured to export TCP sessions records. This achievement represents a cornerstone of a 100 GbE FPGA flow exporter design, that aims for supporting in the order of tens of millions concurrent flows.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130145142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Proposal of Two Histogram Circuits to Calculate Similarities between Video Frames Using FPGAs 利用fpga计算视频帧间相似度的两种直方图电路
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/SPL.2019.8714375
S. Geninatti, E. Boemo
{"title":"A Proposal of Two Histogram Circuits to Calculate Similarities between Video Frames Using FPGAs","authors":"S. Geninatti, E. Boemo","doi":"10.1109/SPL.2019.8714375","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714375","url":null,"abstract":"This paper describes two hardware schemes for calculating luminosity histograms using FPGAs. The first circuit makes extensive use of the embedded RAM blocks present in many FPGA models. The second alternative is a parallel structure of accomulators that can be easyly adapted to any input bus width. During the histogram computation, each processed pixel increments the value of the register corresponding to its luminance level. Therefore, if several pixels are evaluated at the same time, writing conflicts can be generated when a specific luminosity register is updated by more than one pixel. In the two proposed architectures these collision problems are eliminated. The calculation is made directly from the DC coefficients of the compressed video. This fact minimizes data bandwidth per frame, allowing a fast determination of similarity. The presented histogram circuits are part of an FPGA-based custom processor to calculate the similarity between two video frames by cross-correlating their histograms.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131852941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware Implementation of a Multi-Channel EEG Lossless Compression Algorithm 多通道脑电信号无损压缩算法的硬件实现
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/SPL.2019.8714388
Federico Favaro, Juan Pablo Oliver
{"title":"Hardware Implementation of a Multi-Channel EEG Lossless Compression Algorithm","authors":"Federico Favaro, Juan Pablo Oliver","doi":"10.1109/SPL.2019.8714388","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714388","url":null,"abstract":"This paper presents a hardware implementation of a multi-channel EEG lossless compression algorithm. The design is the first step in the development of a low power, wireless recording system for the acquisition of EEG signals. It was written in VHDL and tested in a Cyclone V FPGA. The validation was fulfilled using simulations, comparing the compressed output against one obtained with the software version of the algorithm written in C. For 21 channels, 16 bit per sample and using a 50 MHz clock, it achieved an average compression time per sample of $pmb{0.52} mu s$, and an average power consumption of 10 mW per channel.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114150963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High-Speed Serial Protocol Multi-Link and Multi-Stage for FPGAs fpga的多链路多级高速串行协议
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/SPL.2019.8714335
D. M. Caruso, Andrés M. Airabella, R. Melo
{"title":"High-Speed Serial Protocol Multi-Link and Multi-Stage for FPGAs","authors":"D. M. Caruso, Andrés M. Airabella, R. Melo","doi":"10.1109/SPL.2019.8714335","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714335","url":null,"abstract":"This work presents a high-speed communication link implementation for a high-resolution camera used in a low earth orbit (LEO) satellite, that was already in space. The whole acquisition system involves three Microsemi FPGAs that move a great amount of data over a multi-link high-speed serial channel. The implementation of a custom protocol is proposed to perform a point-to-point communication. To validate the proposal, tests on hardware are presented, reaching an average speed up to 2.96 Gbps. Finally, the proposed design is compared with other proprietary solution from Microsemi, highlighting the pros and cons of each one. The protocol presented in this work, was implemented and it has worked successfully in space.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128351966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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