An Application of the Hardened Floating-Point Cores on HIL Simulations

Abstract

Programmable logic is becoming usual in Hardware-In-the-Loop (HIL) emulation due to its acceleration capabilities. HIL technique is specifically useful for verifying power electronics. But even using programmable logic, if integration steps below 100 ns are required and floating-point is the chosen representation, it has not been possible to reach real time simulations. With the release of devices with HFP (Hardened Floating-Point) cores -dedicated floating-point blocks implemented in silicon-, the minimum achievable simulation step decreases significantly. This work shows an implementation of a full-bridge converter model using HFP cores. Results show that the HFP-based model achieve a simulation step around 10 ns in this case. However, when decreasing the integration step, numerical resolution can become an issue. Thus, designers face a trade-off before selecting 32-bit floating-point representation for a model: better integration steps vs. accuracy limits. In this way, resolution and accuracy are also studied.