Pipelining on FPGAs: A Tutorial

Abstract

This tutorial reviews historical milestones and main concepts regarding the pipelining of electronic circuits. Although the technique emerged in the 1960s, it remains a direct way to simultaneously increase throughput and reduce power in FPGA-based systems. However, the efficacy of pipelining is limited by the dominance of register and routing delays. This work focuses on bit-level pipelining. It analyses by examples keys aspects such as construction hints, pipeline metrics, effects of registering, preferential pipeline directions, and synchronization failures. The text condenses the first section of the invited tutorial lecture at the 2019 Southern Conference on Programmable Logic (SPL). Whenever is possible, numeric examples are particularized to FPGA technology, but in some cases, cell-based ASICs data are deemed more convenient. The ideas would be useful for students of an advanced course on digital electronics, or PhD candidates interested in the details of the design of integrated circuits.