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2019 X Southern Conference on Programmable Logic (SPL)最新文献

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Implementation of Search Process for a Content-Based Image Retrieval Application on System on Chip 基于内容的图像检索在片上系统的实现
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/SPL.2019.8714320
R. Molina, Fernando Rincón Calle, J. D. Dondo Gazzano, R. Petrino, Juan Carlos Lopez Lopez
{"title":"Implementation of Search Process for a Content-Based Image Retrieval Application on System on Chip","authors":"R. Molina, Fernando Rincón Calle, J. D. Dondo Gazzano, R. Petrino, Juan Carlos Lopez Lopez","doi":"10.1109/SPL.2019.8714320","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714320","url":null,"abstract":"The amount of multimedia information on digital platforms has been increasing over the years. Social networks and the advancement of technology have been a determining factor for this event. Due to this fact, the organization, qualification and handling of this type of information has become indispensable, as well as assuring the user the quality of the service in content and execution time in the retrieval of information. This paper presents the implementation of the search process of a content-based image retrieval system, using metric spaces to perform the search and recovery of the image. The high level synthesis is used to development the IP block that will carry out the recovery process in the programmable logic. The experiments are performed on a PYNQ-Z1 board from $mathbf{Xillinx}bigcirc!!!!!!{mathrm{c}}$ and on a CPU $mathbf{Intel}bigcirc!!!!!!{mathrm{c}}$ Core i5 7th generation. The effectiveness of the implementation is supported by the results obtained.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129647003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Flexible Software to Hardware Migration Methodology for FPGA Design and Verification FPGA设计与验证的灵活软硬件迁移方法
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/SPL.2019.8714377
Matias Trapaglia, R. Cayssials, L. de Pasquale, E. Ferro
{"title":"Flexible Software to Hardware Migration Methodology for FPGA Design and Verification","authors":"Matias Trapaglia, R. Cayssials, L. de Pasquale, E. Ferro","doi":"10.1109/SPL.2019.8714377","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714377","url":null,"abstract":"Modern FPGA developments require flexible and Agile methodologies to support complex designs meeting the current highly demanding time-to-market metrics. Traditional hardware development processes based on waterfall flows are not adequate to get the most of the new reconfigurable FPGA technologies. Co-design and co-verification techniques allow handling both software and hardware development in a highly integrated process. However, such integration requires a deep knowledge of both hardware and software development. DUTILS is a Python/Cocotb-based environment for concurrent development suitable for modern software development technologies. This paper proposes software to hardware migration methodology for the DUTILS environment that allows a seamless integration between software and hardware design and the verification process flow of the whole system.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"8 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120851461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
[Back cover - Organizers & Sponsors] [封底-主办单位及赞助商]
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/spl.2019.8714196
{"title":"[Back cover - Organizers & Sponsors]","authors":"","doi":"10.1109/spl.2019.8714196","DOIUrl":"https://doi.org/10.1109/spl.2019.8714196","url":null,"abstract":"","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129989325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Real Time Adaptive Template Matching Algorithm in UAV Navigation Using a SoC System 基于SoC系统的无人机导航实时自适应模板匹配算法
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/SPL.2019.8714333
Alex Gonçalves Saraiva, O. Saotome, Roberto D'Amore, Élcio Shiguemori
{"title":"A Real Time Adaptive Template Matching Algorithm in UAV Navigation Using a SoC System","authors":"Alex Gonçalves Saraiva, O. Saotome, Roberto D'Amore, Élcio Shiguemori","doi":"10.1109/SPL.2019.8714333","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714333","url":null,"abstract":"Computer vision techniques employing convolution techniques are widely used to identify objects and patterns in images. This work describes an Adaptive Template Matching algorithm for tracking marks in videos. A SoC implementation is also presented for a non-adaptive case. The window used for searching a template is reduced, presuming that the template should not be far from its location in the previous frame. The proposed algorithm allows the identification through Normalized Cross-Correlation metric. The initial proposal is a computer-based implementation using computer vision libraries. As an alternative for the high time of processing, an alternative SoC implementation is presented. The results show the achievement of a real time condition for an UAV navigation application.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"205 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120901019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SPL 2019 Organization SPL 2019组织
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/spl.2019.8714569
{"title":"SPL 2019 Organization","authors":"","doi":"10.1109/spl.2019.8714569","DOIUrl":"https://doi.org/10.1109/spl.2019.8714569","url":null,"abstract":"","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122374806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Prologue 序言
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/spl.2019.8714303
{"title":"Prologue","authors":"","doi":"10.1109/spl.2019.8714303","DOIUrl":"https://doi.org/10.1109/spl.2019.8714303","url":null,"abstract":"","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124411211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-Performance Architectures for Finite Field Inversion Over GF(2163) GF(2163)有限场反演的高性能架构
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/SPL.2019.8714372
Paulo Realpe-Muñoz, Guillermo David-Núñez, Jaime Velasco-Medina
{"title":"High-Performance Architectures for Finite Field Inversion Over GF(2163)","authors":"Paulo Realpe-Muñoz, Guillermo David-Núñez, Jaime Velasco-Medina","doi":"10.1109/SPL.2019.8714372","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714372","url":null,"abstract":"Inversion is the most computationally expensive finite field operation in public-key cryptographic such as elliptic curve cryptography (ECC). This paper presents highperformance architectures for performing the finite field inversion using Gaussian Normal Bases (GNB) and a digit-level serial-in parallel-out multiplier (DL-SIPO) over GF(2163). We propose three architectures to carry out the inversion operation. The first one is based on classic Itoh-Tsujji Algorithm (ITA), the second one carries out the inversion operation according to the NIST binary fields over GF $(2^{163})$ and finally, the last one is based on Fermat's Little Theorem (FLT). The architectures were designed using VHDL description, synthesized on the Stratix IV FPGA using Quartus Prime 17.0, and verified in ModelSim and Matlab. The synthesis results show that the designed architectures present a very good performance using low area. In this case, the processing time and area resources to compute the inversion operation were 114.2, 115.9 and 114.5 ns using 11624, 11558 and 11690 LUTs, respectively.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130625313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design, Simulation, Implementation and Testing of Search and Tracking Modules for a FPGA-Based GPS Receiver 基于fpga的GPS接收机搜索与跟踪模块的设计、仿真、实现与测试
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/SPL.2019.8714299
F. S. Larosa
{"title":"Design, Simulation, Implementation and Testing of Search and Tracking Modules for a FPGA-Based GPS Receiver","authors":"F. S. Larosa","doi":"10.1109/SPL.2019.8714299","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714299","url":null,"abstract":"GPS receivers constitute a topic of great importance since they have application in many fields of science and industry as geodesy, aviation, security and defense to name a few. The understanding of their internals, including the nature of signals and the algorithms involved in their processing are crucial in the development of customized receivers. In this work, development, simulation and testing of search and tracking modules on a field programmable gate array (FPGA) is presented. Additionally, the architecture of the proposed system is presented along with front end design and implementation. This work presents a low-resource, low-level portable implementation approach that can be easily scaled up.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131873506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
FPGA Based Wide Range Neutron Flux Monitoring System Using Campbell Mode 基于FPGA的Campbell模式宽范围中子通量监测系统
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/SPL.2019.8714252
Juan Alarcón, Leandro Marzano, S. Thorp, C. Verrastro
{"title":"FPGA Based Wide Range Neutron Flux Monitoring System Using Campbell Mode","authors":"Juan Alarcón, Leandro Marzano, S. Thorp, C. Verrastro","doi":"10.1109/SPL.2019.8714252","DOIUrl":"https://doi.org/10.1109/SPL.2019.8714252","url":null,"abstract":"Neutron flux monitoring in research reactors can range from shutdown to full power over 10 to 12 decades. At low power, neutron flux is usually measured with proportional counters in pulse mode. The detector is moved away from high flux zones to avoid pulse saturation until ionization chambers are in range. Campbell mode allows to make a measurement using a single detector able to cover the entire operating range. This work presents an FPGA-based system that implements Campbell mode operation. The system prototype was successfully tested in the CNEA RA-3 research and production reactor at Ezeiza Atomic Center.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"21 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126044105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
2019 X Southern Conference on Programmable Logic (SPL) 2019 X南方可编程逻辑会议(SPL)
2019 X Southern Conference on Programmable Logic (SPL) Pub Date : 2019-04-01 DOI: 10.1109/spl.2019.8714563
Cayssials, Ricardo, R. Melo, E. Todorovich, compilado por Ricardo Cayssials
{"title":"2019 X Southern Conference on Programmable Logic (SPL)","authors":"Cayssials, Ricardo, R. Melo, E. Todorovich, compilado por Ricardo Cayssials","doi":"10.1109/spl.2019.8714563","DOIUrl":"https://doi.org/10.1109/spl.2019.8714563","url":null,"abstract":"El trabajo presenta el desarrollo e implementación de un generador de baud rate basado en un divisor fraccional, con el objetivo de resolver un problema especı́fico: disponer de UARTs con tasas iguales o superiores a 230400 bps, y un reloj de sistema que no es múltiplo entero de éstas velocidades. Bajo estas condiciones, el error que genera un divisor de frecuencia digital simple excede lo tolerable en una comunicación serie ası́ncrona. Se presenta la teorı́a del divisor fraccional, las consideraciones de diseño, el proceso de desarrollo, los resultados de la implementación del generador sobre una FPGA, y las ventajas de uso del divisor fraccional.","PeriodicalId":161898,"journal":{"name":"2019 X Southern Conference on Programmable Logic (SPL)","volume":"25 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116550548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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