A Proposal of Two Histogram Circuits to Calculate Similarities between Video Frames Using FPGAs

This paper describes two hardware schemes for calculating luminosity histograms using FPGAs. The first circuit makes extensive use of the embedded RAM blocks present in many FPGA models. The second alternative is a parallel structure of accomulators that can be easyly adapted to any input bus width. During the histogram computation, each processed pixel increments the value of the register corresponding to its luminance level. Therefore, if several pixels are evaluated at the same time, writing conflicts can be generated when a specific luminosity register is updated by more than one pixel. In the two proposed architectures these collision problems are eliminated. The calculation is made directly from the DC coefficients of the compressed video. This fact minimizes data bandwidth per frame, allowing a fast determination of similarity. The presented histogram circuits are part of an FPGA-based custom processor to calculate the similarity between two video frames by cross-correlating their histograms.