Hardware Implementation of a Multi-Channel EEG Lossless Compression Algorithm

This paper presents a hardware implementation of a multi-channel EEG lossless compression algorithm. The design is the first step in the development of a low power, wireless recording system for the acquisition of EEG signals. It was written in VHDL and tested in a Cyclone V FPGA. The validation was fulfilled using simulations, comparing the compressed output against one obtained with the software version of the algorithm written in C. For 21 channels, 16 bit per sample and using a 50 MHz clock, it achieved an average compression time per sample of $\pmb{0.52} \mu s$, and an average power consumption of 10 mW per channel.