Proceedings of the 2020 International Symposium on Physical Design最新文献

{"title":"Physical Design for 3D Chiplets and System Integration","authors":"Cliff Hou","doi":"10.1145/3372780.3378167","DOIUrl":"https://doi.org/10.1145/3372780.3378167","url":null,"abstract":"The convergence of 5G and Artificial Intelligence (AI) that covers the gamut from cloud data centers through network routers to edge applications is poised to open possibilities beyond our imagination and transform how we will go about our daily lives. As the foundational technology supporting 5G and AI innovation, semiconductors strive for greater system performance and broader bandwidth, while increasing functionality and lowering cost. In response, device innovation is transitioning from SoCs to 3D chiplets that combine advanced wafer-level system integration (WLSI) technologies such as CoWoS® (Chip on Wafer on Substrate), Integrated Fan-Out (InFO), Wafer-on-Wafer (WoW) and System-on-Integrated-Chips (SoIC), to enable system integration that meets these demands. Designing 3D chiplets and housing various chips on wafer-level for system integration creates a whole new set of challenges. These start with design partitioning and include handling interfaces between or passing through chips, design for testing (DFT), thermal dissipation, databases and tools integration for chip and packaging design, new IO/ESD (electrostatic discharge), simulation run time and tool capacity, among others. Considering current capabilities and constraints, divide-and-conquer remains the most feasible approach for 3D chiplet design and packaging. Chiplet design needs to integrate data bases and tools with packaging environments for both verification and optimization. Leveraging existing 2D physical design solutions and chip-level abstraction can help meet 3D verification and optimization requirements. The IC industry also needs more DFT and thermal dissipation innovation, especially the latter one. Thermal optimization is critical to 3D chiplets and system integration. The current thermal solution only covers thermal analysis + system-level thermal dissipation. It should start at the IPs and across chip design process, i.e., thermal-aware 3D IC design, to cover IP, macros, and transistors. This speech will address these and other challenges, then propose physical design solutions for 3D chiplets and system integration. CCS CONCEPTS - VLSI design, 3D integrated circuits, VLSI system specification and constraints, and VLSI packaging KEYWORDS Physical design, 3D chiplets and system integration, thermal optimization BIOGRAPHY Dr. Cliff Hou was appointed Vice President of Research and Development at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) in 2011. Since 1999, he has worked to establish node-specific reference flows from 0.13μm to today's leading-edge 3nm at TSMC. Dr. Hou also led TSMC's in-house IP development teams from 2008 to 2010. He is now spearheading TSMC's efforts to build total platform solutions for the industry's high growth markets in Mobile, IoT, Automotive, and High-Performance Computing. Dr. Hou holds 44 U.S. Patents and serves as a member of Board of Directors in Global Unichip Corp. He received B.S. degree in Control Engineering from Taiwan's Nat","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117350198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network","authors":"Rongjian Liang, Hua Xiang, Diwesh Pandey, L. Reddy, Shyam Ramji, Gi-Joon Nam, Jiang Hu","doi":"10.1145/3372780.3375560","DOIUrl":"https://doi.org/10.1145/3372780.3375560","url":null,"abstract":"As the semiconductor process technology advances into sub-10nm regime, cell pin accessibility, which is a complex joint effect from the pin shape and nearby blockages, becomes a main cause for DRC violations. Therefore, a machine learning model for DRC hotspot prediction needs to consider both very high-resolution pin shape patterns and low-resolution layout information as input features. A new convolutional neural network technique, J-Net, is introduced for the prediction with mixed resolution features. This is a customized architecture that is flexible for handling various input and output resolution requirements. It can be applied at placement stage without using global routing information. This technique is evaluated on 12 industrial designs at 7nm technology node. The results show that it can improve true positive rate by 37%, 40% and 14% respectively, compared to three recent works, with similar false positive rates.","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"9 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129773067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs","authors":"Heechun Park, B. W. Ku, Kyungwook Chang, D. Shim, S. Lim","doi":"10.1145/3372780.3375567","DOIUrl":"https://doi.org/10.1145/3372780.3375567","url":null,"abstract":"Despite the recent academic efforts to develop Electronic Design Automation (EDA) algorithms for 3D ICs, the current market does not have commercial 3D computer-aided design (CAD) tools. Insteadpseudo-3D alternative design flows have been devised which utilize commercial 2D CAD engines with tricks that help them operate as a fairly-efficient 3D CAD tool. In this paper we provide detailed discussions and fair power-performance-area (PPA) comparisons of state-of-the-art pseudo-3D design flows. We also analyze the limitations of each design flow and provide solutions with better PPA and various design options. Our experiments using commercial PDK, GDS layouts, and sign-off simulations demonstrate that we achieve up to 26% wirelength and 10% power consumption reduction for pseudo-3D design flows. We also provide a partitioning-first scheme to partitioning-last design flow which increases design freedom with tolerable PPA degradation.","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114566657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Session details: Keynote 1","authors":"W. Swartz","doi":"10.1145/3389215","DOIUrl":"https://doi.org/10.1145/3389215","url":null,"abstract":"","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130306501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advances in Carbon Nanotube Technologies: From Transistors to a RISC-V Microprocessor","authors":"G. Hills, C. Lau, T. Srimani, M. Bishop, P. Kanhaiya, R. Ho, A. Amer, M. Shulaker","doi":"10.1145/3372780.3378170","DOIUrl":"https://doi.org/10.1145/3372780.3378170","url":null,"abstract":"Carbon nanotube (CNT) field-effect transistors (CNFETs) promise to improve the energy efficiency of very-large-scale integrated (VLSI) systems. However, multiple challenges have prevented VLSI CNFET circuits from being realized, including inherent nano-scale material defects, robust processing for yielding complementary CNFETs (i.e., CNT CMOS: including both PMOS and NMOS CNFETs), and major CNT variations. Here, we summarize techniques that we have recently developed to overcome these outstanding challenges, enabling VLSI CNFET circuits to be experimentally realized today using standard VLSI processing and design flows. Leveraging these techniques, we demonstrate the most complex CNFET circuits and systems to-date, including a three-dimensional (3D) imaging system comprising CNFETs fabricated directly on top of a silicon imager, CNT CMOS analog and mixed-signal circuits, 1 kilobit CNFET static random-access memory (SRAM) memory arrays, and a 16-bit RISC-V microprocessor built entirely out of CNFETs.","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"93 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133847098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Session details: Keynote 2","authors":"M. Lin","doi":"10.1145/3389219","DOIUrl":"https://doi.org/10.1145/3389219","url":null,"abstract":"","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131943465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Physical Verification at Advanced Technology Nodes and the Road Ahead","authors":"J. Rey","doi":"10.1145/3372780.3378168","DOIUrl":"https://doi.org/10.1145/3372780.3378168","url":null,"abstract":"In spite of \"doomsday\" expectations, Moore's Law is alive and well. Semiconductor manufacturing and design companies, as well as the Electronic Design Automation (EDA) industry have been pushing ahead to bring more functionality to satisfy more aggressive space/power/performance requirements. Physical verification occupies a unique space in the ecosystem as one of the key bridges between design and manufacturing. As such, the traditional space of design rule checking (DRC) and layout versus schematic (LVS) have expanded into electrical verification and yield enabling technologies such as optical proximity correction, critical area analysis, multi-patterning decomposition and automated filling. To achieve the expected accuracy and performance demanded by the design and manufacturing community, it is necessary to consider the physical effects of the manufacturing processes and electronic devices and to use the most advanced software engineering technology and computational capabilities.","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131093291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Scalable System and Silicon Architectures to Handle the Workloads of the Post-Moore Era","authors":"I. Bolsens","doi":"10.1145/3372780.3378166","DOIUrl":"https://doi.org/10.1145/3372780.3378166","url":null,"abstract":"The end of Moore's law has been proclaimed on many occasions and it's probably safe to say that we are now working in the post-Moore era. But no one is ready to slow down just yet. We can view Gordon Moore's observation on transistor densification as just one aspect of a longer-term underlying technological trend - the Law of Accelerating Returns articulated by Kurzweil. Arguably, companies became somewhat complacent in the Moore era, happy to settle for the gains brought by each new process node. Although we can expect scaling to continue, albeit at a slower pace, the end of Moore's Law delivers a stronger incentive to push other trends of technology progress harder. Some exciting new technologies are now emerging such as multi-chip 3D integration and the introduction of new technologies such as storage-class memory and silicon photonics. Moreover, we are also entering a golden age of computer architecture innovation. One of the key drivers is the pursuit of domain-specific architectures as proclaimed by Turing award winners John Hennessy and David Patterson. A good example is the Xilinx's AI Engine, one of the important features of the Versal? ACAP (adaptive compute acceleration platform) [1]. Today, the explosion of AI workloads is one of the most powerful drivers shifting our attention to find faster ways of moving data into, across, and out of accelerators. Features such as massive parallel processing elements, the use of domain specific accelerators, the dense interconnect between distributed on-chip memories and processing elements, are examples of the ways chip makers are looking beyond scaling to achieve next-generation performance gains. Next, the growing demands of scaling-out hyperscale datacenter applications drive much of the new architecture developments. Given a high diversification of workloads that invoke massive compute and data movement, datacenter architectures are moving away from rigid CPU-centric structures and instead prioritize adaptability and configurability to optimize resources such as memory and connectivity of accelerators assigned to individual workloads. There is no longer a single figure of merit. It's not all about Tera-OPS. Other metrics such as transfers-per-second and latency come to the fore as demands become more real-time; autonomous vehicles being an obvious and important example. Moreover, the transition to 5G will result in solutions that operate across the traditional boundaries between the cloud and edge and embedded platforms that are obviously power-conscious and cost-sensitive. Future workloads will require agile software flows that accommodate the spread of functions across edge and cloud. Another industry megatrend that will drive technology requirements especially in encryption, data storage and communication, is Blockchain. To some, it may already have a bad reputation, tarnished by association with the anarchy of cryptocurrency, but it will be more widely relevant than many of us realize. Who","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122690653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Proceedings of the 2020 International Symposium on Physical Design","authors":"","doi":"10.1145/3372780","DOIUrl":"https://doi.org/10.1145/3372780","url":null,"abstract":"","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124958446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation","authors":"A. Stefanidis, Dimitrios Mangiras, C. Nicopoulos, D. Chinnery, G. Dimitrakopoulos","doi":"10.1145/3372780.3375566","DOIUrl":"https://doi.org/10.1145/3372780.3375566","url":null,"abstract":"Design optimization modifies a netlist with the goal of satisfying the timing constraints at the minimum area and leakage power, without violating any slew or load capacitance constraints. Lagrangian relaxation (LR) based optimization has been established as a viable approach for this. We extend LR-based optimization by interleaving in each iteration techniques such as: gate and flip-flop sizing; buffering to fix late and early timing violations; pin swapping; and useful clock skew. Locally optimal decisions are made using LR-based cost functions, without the need for incremental timing updates. Sub-steps are applied in a balanced manner, accounting for the expected savings and any conflicting timing violations, maximizing the final quality of results under multiple process/operating corners with a reasonable runtime. Experimental results show that our approach achieves better timing, and both lower area and leakage power than the winner of the TAU 2019 contest, on those benchmarks.","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128454503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}