Physical Design for 3D Chiplets and System Integration

Abstract

The convergence of 5G and Artificial Intelligence (AI) that covers the gamut from cloud data centers through network routers to edge applications is poised to open possibilities beyond our imagination and transform how we will go about our daily lives. As the foundational technology supporting 5G and AI innovation, semiconductors strive for greater system performance and broader bandwidth, while increasing functionality and lowering cost. In response, device innovation is transitioning from SoCs to 3D chiplets that combine advanced wafer-level system integration (WLSI) technologies such as CoWoS® (Chip on Wafer on Substrate), Integrated Fan-Out (InFO), Wafer-on-Wafer (WoW) and System-on-Integrated-Chips (SoIC), to enable system integration that meets these demands. Designing 3D chiplets and housing various chips on wafer-level for system integration creates a whole new set of challenges. These start with design partitioning and include handling interfaces between or passing through chips, design for testing (DFT), thermal dissipation, databases and tools integration for chip and packaging design, new IO/ESD (electrostatic discharge), simulation run time and tool capacity, among others. Considering current capabilities and constraints, divide-and-conquer remains the most feasible approach for 3D chiplet design and packaging. Chiplet design needs to integrate data bases and tools with packaging environments for both verification and optimization. Leveraging existing 2D physical design solutions and chip-level abstraction can help meet 3D verification and optimization requirements. The IC industry also needs more DFT and thermal dissipation innovation, especially the latter one. Thermal optimization is critical to 3D chiplets and system integration. The current thermal solution only covers thermal analysis + system-level thermal dissipation. It should start at the IPs and across chip design process, i.e., thermal-aware 3D IC design, to cover IP, macros, and transistors. This speech will address these and other challenges, then propose physical design solutions for 3D chiplets and system integration. CCS CONCEPTS - VLSI design, 3D integrated circuits, VLSI system specification and constraints, and VLSI packaging KEYWORDS Physical design, 3D chiplets and system integration, thermal optimization BIOGRAPHY Dr. Cliff Hou was appointed Vice President of Research and Development at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) in 2011. Since 1999, he has worked to establish node-specific reference flows from 0.13μm to today's leading-edge 3nm at TSMC. Dr. Hou also led TSMC's in-house IP development teams from 2008 to 2010. He is now spearheading TSMC's efforts to build total platform solutions for the industry's high growth markets in Mobile, IoT, Automotive, and High-Performance Computing. Dr. Hou holds 44 U.S. Patents and serves as a member of Board of Directors in Global Unichip Corp. He received B.S. degree in Control Engineering from Taiwan's National Chiao-Tung University, and Ph.D. in Electrical and Computer Engineering from Syracuse University.