Proceedings of the 2020 International Symposium on Physical Design最新文献

Selective Sensor Placement for Cost-Effective Online Aging Monitoring and Resilience 具有成本效益的在线老化监测和恢复的选择性传感器放置

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3372780.3375556

Hao-Chun Chang, Li-An Huang, Kai-Chiang Wu, Yu-Guang Chen

引用次数: 0

Session details: Session 6: Machine Learning for Physical Design (part 2) 会议详情:第6部分:物理设计中的机器学习(第二部分)

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3389222

Ismail Bustany

引用次数: 0

Learning from Experience: Applying ML to Analog Circuit Design 从经验中学习:将机器学习应用于模拟电路设计

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3372780.3378172

K. Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, A. Sharma, Wenbin Xu, S. Burns, R. Harjani, Jiang Hu, P. Mukherjee, S. Sapatnekar

{"title":"Learning from Experience: Applying ML to Analog Circuit Design","authors":"K. Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, A. Sharma, Wenbin Xu, S. Burns, R. Harjani, Jiang Hu, P. Mukherjee, S. Sapatnekar","doi":"10.1145/3372780.3378172","DOIUrl":"https://doi.org/10.1145/3372780.3378172","url":null,"abstract":"The problem of analog design automation has vexed several generations of researchers in electronic design automation. At its core, the difficulty of the problem is related to the fact that machinegenerated designs have been unable to match the quality of the human designer. The human designer typically recognizes blocks from a netlist and draws upon her/his experience to translate these blocks into a circuit that is laid out in silicon. The ability to annotate blocks in a schematic or netlist-level description of a circuit is key to this entire process, but it is a process fraught with complexity due to the large number of variants of each circuit type. For example, the number of topologies of operational transconductance amplifiers (OTAs) easily numbers in the hundreds. A designer manages this complexity by dividing this large set of variants into classes (e.g., OTAs may be telescopic, folded cascode, etc.). Even so, the number of minor variations within each class is large. Early approaches to analog design automation attempted to use rule-based methods to capture these variations, but this database of rules required tender care: each new variant might require a new rule. As machine learning (ML) based alternatives have become more viable, alternative forms of solving this problem have begun to be explored. Our effort is part of the ALIGN (Analog Layout, Intelligently Generated from Netlists) project [2, 3], which is developing opensource software for analog/mixed-signal circuit layout [1]. Our specific goal is to translate a netlist into a physical layout, with 24-hour turnaround and no human in the loop. The ALIGN flow inputs a netlist whose topology and transistor sizes have already been chosen, a set of performance specifications, and a process design kit (PDK) that defines the process technology. The output of ALIGN is a layout in GDSII format.","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133917209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Session details: Session 4: Circuit Design and Security 会议详情:会议4:电路设计和安全

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3389220

D. Chinnery

引用次数: 0

Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs 全片面对面键合3D集成电路的电热耦合提取与分析

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3372780.3378169

Lingjun Zhu, Kyungwook Chang, D. Petranovic, S. Sinha, Y. Yu, S. Lim

引用次数: 2

Hill Climbing with Trees: Detail Placement for Large Windows 爬树:大窗户的细节放置

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3372780.3375563

M. Khasawneh, P. Madden

引用次数: 3

Understanding Graphs in EDA: From Shallow to Deep Learning 理解EDA中的图:从浅学习到深度学习

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3372780.3378173

Yuzhe Ma, Zhuolun He, Wei Li, Lu Zhang, Bei Yu

引用次数: 26

ISPD 2020 Physical Mapping of Neural Networks on a Wafer-Scale Deep Learning Accelerator

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3372780.3380846

Michael James, Marvin Tom, P. Groeneveld, V. Kibardin

{"title":"ISPD 2020 Physical Mapping of Neural Networks on a Wafer-Scale Deep Learning Accelerator","authors":"Michael James, Marvin Tom, P. Groeneveld, V. Kibardin","doi":"10.1145/3372780.3380846","DOIUrl":"https://doi.org/10.1145/3372780.3380846","url":null,"abstract":"This paper introduces a special case of the floorplanning problem for optimizing neural networks to run on a wafer-scale computing engine. From a compute perspective, neural networks can be represented by a deeply layered structure of compute kernels. During the training of a neural network, gradient descent is used to determine the weight factors. Each layer then uses a local weight tensor to transform \"activations\" and \"gradients\" that are shared among connected kernels according to the topology of the network. This process is computationally intensive and requires high memory and communication bandwidth. Cerebras has developed a novel computer system designed for this work that is powered by a 21.5cm by 21.5cm wafer-scale processor with 400,000 programmable compute cores. It is structured as a regular array of 633 by 633 processing elements, each with its own local high bandwidth SRAM memory and direct high bandwidth connection to its neighboring cores. In addition to supporting traditional execution models for neural network training and inference, this engine has a unique capability to compile and compute every layer of a complete neural network simultaneously. Mapping a neural network in this fashion onto Cerebras' Wafer-Scale Engine (WSE) is reminiscent of the traditional floorplanning problem in physical design. A kernel ends up as a rectangle of x by y compute elements. These are the flexible blocks that need to be placed to optimize performance. This paper describes an ISPD 2020 challenge to develop algorithms and heuristics that produce compiled neural networks that achieve the highest possible performance on the Cerebras WSE.","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130347519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Session details: Session 2: Breaking New Ground: From Carbon Nanotubes to Packaging 会议详情:第二部分:开拓新领域:从碳纳米管到包装

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3389217

P. Madden

引用次数: 0

Session details: Session 8: ISPD 2020 Contest Results and Poster Presentations 会议详情:第8部分:ISPD 2020竞赛结果和海报展示

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3389224

Marvin Tom

引用次数: 0