Proceedings of the 2020 International Symposium on Physical Design最新文献_第2页

TEMPO: Fast Mask Topography Effect Modeling with Deep Learning TEMPO:基于深度学习的快速掩膜地形效应建模

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3372780.3375565

Wei Ye, M. Alawieh, Yuki Watanabe, S. Nojima, Yibo Lin, D. Pan

{"title":"TEMPO: Fast Mask Topography Effect Modeling with Deep Learning","authors":"Wei Ye, M. Alawieh, Yuki Watanabe, S. Nojima, Yibo Lin, D. Pan","doi":"10.1145/3372780.3375565","DOIUrl":"https://doi.org/10.1145/3372780.3375565","url":null,"abstract":"With the continuous shrinking of the semiconductor device dimensions, mask topography effects stand out among the major factors influencing the lithography process. Including these effects in the lithography optimization procedure has become necessary for advanced technology nodes. However, conventional rigorous simulation for mask topography effects is extremely computationally expensive for high accuracy. In this work, we propose TEMPO as a novel generative learning-based framework for efficient and accurate 3D aerial image prediction. At its core, TEMPO comprises a generative adversarial network capable of predicting aerial image intensity at different resist heights. Compared to the default approach of building a unique model for each desired height, TEMPO takes as one of its inputs the desired height to produce the corresponding aerial image. In this way, the global model in TEMPO can capture the shared behavior among different heights, thus, resulting in smaller model size. Besides, across-height information sharing results in better model accuracy and generalization capability. Our experimental results demonstrate that TEMPO can obtain up to 1170x speedup compared with rigorous simulation while achieving satisfactory accuracy.","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123374263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Session details: Session 1: Placement 会话详细信息:会话1:安置

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3389216

Stephen Yang

引用次数: 0

Synthesis of Clock Networks with a Mode Reconfigurable Topology and No Short Circuit Current 具有模式可重构拓扑和无短路电流的时钟网络的综合

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3372780.3375559

Necati Uysal, Juan A. Cabrera, Rickard Ewetz

{"title":"Synthesis of Clock Networks with a Mode Reconfigurable Topology and No Short Circuit Current","authors":"Necati Uysal, Juan A. Cabrera, Rickard Ewetz","doi":"10.1145/3372780.3375559","DOIUrl":"https://doi.org/10.1145/3372780.3375559","url":null,"abstract":"Circuits deployed in the Internet of Things operate in low and high performance modes to cater to variable frequency and power requirements. Consequently, the clock networks for such circuits must be synthesized meeting drastically different timing constraints under variations in the different modes. The overall power consumption and robustness to variations of a clock network is determined by the topology. However, state-of-the-art clock networks use the same topology in every mode, despite that the timing constraints in the low and high performance modes are very different. In this paper, we propose a clock network with a mode reconfigurable topology (MRT) for circuits with positive-edge triggered sequential elements. In high performance modes, the required robustness to variations is provided by reconfiguring the MRT structure into a near-tree. In low performance modes, the MRT structure is reconfigured into a tree to save power. Non-tree (or near-tree) structures provide robustness to variations by appropriately constructing multiple alternative paths from the clock source to the clock sinks, which neutralizes the negative impact of variations. In MRT structures, OR-gates are used to join multiple alternative paths into a single path. Consequently, the MRT structures consume no short circuit power because there is only one gate driving each net. Moreover, it is straightforward to reconfigure MRT structures into a tree by gating the clock signal in part of the structure. Compared with state-of-the-art near-tree structures, MRT structures have 8% lower power consumption and similar robustness to variations in high performance modes. In low performance modes, the power consumption is 16% smaller when reconfiguration is used.","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133779434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Session details: Session 3: Machine Learning for Physical Design (part 1) 会议详情:第三部分:物理设计中的机器学习(第一部分)

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3389218

P. Groeneveld

引用次数: 0

Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV 针对时钟诱发OCV的软聚类驱动触发器放置

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3372780.3375564

Dimitrios Mangiras, Pavlos M. Mattheakis, Pierre-Olivier Ribet, G. Dimitrakopoulos

引用次数: 0

Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network 用卷积神经网络将全局路由报告转化为DRC冲突图

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3372780.3375557

Wei-Tse Hung, Jun Huang, Yih-Chih Chou, Cheng-Hong Tsai, M. Chao

{"title":"Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network","authors":"Wei-Tse Hung, Jun Huang, Yih-Chih Chou, Cheng-Hong Tsai, M. Chao","doi":"10.1145/3372780.3375557","DOIUrl":"https://doi.org/10.1145/3372780.3375557","url":null,"abstract":"In this paper, we have proposed a machine-learning framework to predict the DRC-violation map of a given design resulting from its detailed routing based on the congestion report resulting from its global routing. The proposed framework utilizes convolutional neural network as its core technique to train this prediction model. The training dataset is collected from 15 industrial designs using a leading commercial APR tool, and the total number of collected training samples exceed 26M. A specialized under-sampling technique is proposed to select important training samples for learning, compensate for the inaccuracy misled by a highly imbalanced training dataset, and speed up the entire training process. The experimental result demonstrates that our trained model can result in not only a significantly higher accuracy than previous related works but also a DRC violation map visually matching the actual ones closely. The average runtime of using our learned model to generate a DRC-violation map is only 3% of that of global routing, and hence our proposed framework can be viewed as a simple add-on tool to a current commercial global router that can efficiently and effectively generate a more realistic DRC-violation map without really applying detailed routing.","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122728726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Lookahead Placement Optimization with Cell Library-based Pin Accessibility Prediction via Active Learning 基于主动学习的基于Cell库的引脚可及性预测的前瞻放置优化

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3372780.3375562

Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, P. H. Tai, Cindy Chin-Fang Shen, Henry Sheng

{"title":"Lookahead Placement Optimization with Cell Library-based Pin Accessibility Prediction via Active Learning","authors":"Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, P. H. Tai, Cindy Chin-Fang Shen, Henry Sheng","doi":"10.1145/3372780.3375562","DOIUrl":"https://doi.org/10.1145/3372780.3375562","url":null,"abstract":"With the development of advanced process nodes of semiconductor, the problem of pin access has become one of the major factors to impact the occurrences of design rule violations (DRVs) due to complex design rules and limited routing resource. Many state-of-the-art works address the problem of DRV prediction by adopting supervised machine learning approaches. However, those supervised learning approaches extract the labels of training data by generating a great number of routed designs in advance, giving rise to large effort on training data preparation. In addition, the pre-trained model could hardly predict unseen data and thus may not be applied to predict other designs containing cells that are not used in the training data. In this paper, we propose the first work of cell library-based pin accessibility prediction (PAP) by using active learning techniques. A given set of standard cell libraries is served as the only input for model training. Unlike most of existing studies that aim at design-specific training, we propose a library-based model which can be applied to all designs referencing to the same standard cell library set. Experimental results show that the proposed model can be applied to predict two different designs with different reference library sets. The number of remaining DRVs and M2 shorts of the designs optimized by the proposed model are also much fewer than those of design-specific models.","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127933487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Session details: Session 5: Timing and Clocking 会话详细信息:会话5:定时和时钟

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3389221

Evangeline F. Y. Young

引用次数: 0

Via Pillar-aware Detailed Placement 通过柱子感知的详细布局

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3372780.3375561

Yong Zhong, Tao-Chun Yu, Kai-Chuan Yang, Shao-Yun Fang

{"title":"Via Pillar-aware Detailed Placement","authors":"Yong Zhong, Tao-Chun Yu, Kai-Chuan Yang, Shao-Yun Fang","doi":"10.1145/3372780.3375561","DOIUrl":"https://doi.org/10.1145/3372780.3375561","url":null,"abstract":"With the feature size shrinking down to 7 nm and beyond, the impact of wire resistance is significantly growing, and the circuit delay incurred by metal wires is noticeably raising. To address this issue, a new technique called via pillar insertion is developed. However, the poor success rate of the via pillar insertion process immediately becomes an important problem. In this paper, we explore the causes of via pillar insertion failures by experiments on the ISPD 2015 benchmarks, which are embedded with a real industrial cell library. The results show that the reasons for the low success rate may be due to track misalignment, power and ground stripe overlapping, and insufficient margin area. Therefore, we propose the first detailed placement flow which is aware of via pillars to maximize the success rate of via pillar insertion. In the proposed flow, we first filter out infeasible cell rows and then move the via pillar-inserting cells to their eligible positions. Next, we adopt a two-stage legalization method with high flexibility on cell ordering based on a dynamic programming-based detailed placement algorithm. Finally, we improve congested rows with a global moving process. Experiment results show that our algorithm improves the insertion rates by 54-58%, and achieves over 99% insertion rate on average.","PeriodicalId":151741,"journal":{"name":"Proceedings of the 2020 International Symposium on Physical Design","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133694863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Timing Driven Partition for Multi-FPGA Systems with TDM Awareness 具有TDM感知的多fpga系统的时序驱动分区

Proceedings of the 2020 International Symposium on Physical Design Pub Date : 2020-03-30 DOI: 10.1145/3372780.3375558

Sin-Hong Liou, Sean Shih-Ying Liu, Richard Sun, Hung-Ming Chen

引用次数: 4