Timing Driven Partition for Multi-FPGA Systems with TDM Awareness

Abstract

Multi-FPGA system is a popular approach to achieve hardware acceleration with the scalability to accommodate large designs. To overcome the connectivity constraint between each pair of FPGAs, Time-division multiplexing (TDM) is adopted with the expense of additional delay that dominates the performance on multi-FPGA system based emulator. To the best of our knowledge, there is no prior work on partitioning for multi-FPGA system considering hardware configuration and the impact of TDM. This work proposes a partition methodology to improve timing performance for multi-FPGA system. Delay introduced by TDM is estimated and optimized using look-up table for better efficiency. Our experimental result shows 43% improvement in maximum delay while considering both hardware configuration and impact of TDM compared with cut driven partition approach.