Lookahead Placement Optimization with Cell Library-based Pin Accessibility Prediction via Active Learning

With the development of advanced process nodes of semiconductor, the problem of pin access has become one of the major factors to impact the occurrences of design rule violations (DRVs) due to complex design rules and limited routing resource. Many state-of-the-art works address the problem of DRV prediction by adopting supervised machine learning approaches. However, those supervised learning approaches extract the labels of training data by generating a great number of routed designs in advance, giving rise to large effort on training data preparation. In addition, the pre-trained model could hardly predict unseen data and thus may not be applied to predict other designs containing cells that are not used in the training data. In this paper, we propose the first work of cell library-based pin accessibility prediction (PAP) by using active learning techniques. A given set of standard cell libraries is served as the only input for model training. Unlike most of existing studies that aim at design-specific training, we propose a library-based model which can be applied to all designs referencing to the same standard cell library set. Experimental results show that the proposed model can be applied to predict two different designs with different reference library sets. The number of remaining DRVs and M2 shorts of the designs optimized by the proposed model are also much fewer than those of design-specific models.