Via Pillar-aware Detailed Placement

Abstract

With the feature size shrinking down to 7 nm and beyond, the impact of wire resistance is significantly growing, and the circuit delay incurred by metal wires is noticeably raising. To address this issue, a new technique called via pillar insertion is developed. However, the poor success rate of the via pillar insertion process immediately becomes an important problem. In this paper, we explore the causes of via pillar insertion failures by experiments on the ISPD 2015 benchmarks, which are embedded with a real industrial cell library. The results show that the reasons for the low success rate may be due to track misalignment, power and ground stripe overlapping, and insufficient margin area. Therefore, we propose the first detailed placement flow which is aware of via pillars to maximize the success rate of via pillar insertion. In the proposed flow, we first filter out infeasible cell rows and then move the via pillar-inserting cells to their eligible positions. Next, we adopt a two-stage legalization method with high flexibility on cell ordering based on a dynamic programming-based detailed placement algorithm. Finally, we improve congested rows with a global moving process. Experiment results show that our algorithm improves the insertion rates by 54-58%, and achieves over 99% insertion rate on average.