Hill Climbing with Trees: Detail Placement for Large Windows

Abstract

Integrated circuit design encompasses a wide range of intractable optimization problems. In this paper, we extend linear time hill climbing techniques from graph partitioning to address detailed placement -- this results in a new way to refine circuit designs, dramatically expands the size of practical optimization windows, and enables wire length reductions on a variety of benchmark problems. The approach is versatile and straight-forward to implement, allowing it to be applied to a wide range of problems within design automation, and beyond.