{"title":"Optimizing the cleaning process through cleaning efficiency examination","authors":"V. Sítko, M. Saffer, I. Szendiuch, M. Bursik","doi":"10.1109/IEMT.2008.5507814","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507814","url":null,"abstract":"The paper explores the efficiency of cleaning methods in order to select a method and optimize cleaning as a part of assembly manufacturing process in microelectronics. To find out the advantages and potentialities of each single cleaning method it is necessary to use simple but reliable evaluation method. In this paper are under consideration two different methods for contamination evaluation, the first being the standard one using the contaminometer, and the second, new one, which is developed on an optical principle. The new method for cleaning evaluation is based on measuring the contamination in special substrate pattern using a scanning unit (programmable automated optical inspection). The special pattern was designed and realized on a glass substrate with ceramic chip models. The experimental part presents the efficiency examination and compares ultrasonic cleaning in microemulsion to other methods like spray in the air etc. The results of this study are used in optimizing and adjusting cleaning equipments as well as in their improvement and innovation.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124728244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High power multi-chip system integration in package","authors":"H. Wieser, S. Wei, A. Kolbeck","doi":"10.1109/IEMT.2008.5507871","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507871","url":null,"abstract":"This paper presents a new high power package for automotive products. It provides innovative interconnecting concepts for multi-die integration of different semiconductor technologies in a single package with automotive grade reliability. Cost effective thermal performance and current carrying capabilities are improved compared to standard packaging methods. A description of key manufacturing process steps, the resulting package integrity, device performance and reliability will be given during the IEMT conference. Special focus will be on the optimization of the process with mold flow simulations and encapsulation experiments with a split flag design. Applied design and process development methodologies will be demonstrated for an automotive high power dual chip application. Experimental characterization will comprise thermal and electrical performance measurements and environmental stress tests.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126402923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The effect of STI and active length on dual gate oxide reliability","authors":"N. H. Seng","doi":"10.1109/IEMT.2008.5507827","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507827","url":null,"abstract":"Wafer Level Reliability Gate Oxide Integrity tests such as voltage-ramped and constant current stress have been conducted on area plate-type, poly edge and STI edge intensive test structures. The WLR tests are required for qualifying the process of integrating 3.3 nm and 12.5 nm dual gate oxide operated under the bias of 1.8V and 5V respectively on a single chip. It has been found that the Qbd value of nMOS STI edge intensive capacitors for 12.5 nm oxide was nearly one order lower than the rest of the test structure design. Failure analysis using emission microscopy and SEM showed that the oxide breakdown occurred near STI shoulder. The STI effect was evaluated using various active lengths of test structures. The appropriate STI edge intensive test structure for 12.5 nm oxide GOI qualification was designed and verified.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126599189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
U. Hashim, S. Salleh, Emi Azri Shohini, Siti Fatimah Abd Rahman
{"title":"Nanowire conductance biosensor by spacer patterning lithography technique for DNA hybridization detection: Design and fabrication method","authors":"U. Hashim, S. Salleh, Emi Azri Shohini, Siti Fatimah Abd Rahman","doi":"10.1109/IEMT.2008.5507831","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507831","url":null,"abstract":"The use of Silicon nanowires has allowed the introduction of many new signal transduction technologies in biosensors. The sensitivity and performance of biosensors is being improved by using doping process for their construction. This research presents the design and fabrication of a Silicon nanowire for deoxyribonucleic acid (DNA) hybridization detection using electrodes made of nanowires whose width is comparable to the size of a DNA molecule. During hybridization, DNA change from single stranded DNA (ssDNA) to double stranded DNA (dsDNA) cause the change of charge density of molecules structure. Fabrication of a Silicon nanowire (NW) using spacer patterning lithography (SPL) techniques is addressed and characterization of its conductivity altogether with capacitance effect is discussed in this research.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"605 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120880980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High speed wafer dicing with ablation laser cut","authors":"David Wong Chee Way, L. Ying","doi":"10.1109/IEMT.2008.5507855","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507855","url":null,"abstract":"Conventional blade dicing is well known as standard process for semiconductor wafer singulation. As of to-date, wafer technologies employed many changes such as larger wafer diameter, thinner chip ≤ 100μm and heavy metal structure in the saw street. Consequently, unforeseen defects such as longer sawing time lead to wafer bond pad corrosion, chip crack and larger backside chipping arised. Blade dicing can no longer fulfill the demands of new emerging types of semiconductor devices. New chips separation methods are investigated here. Laser cutting is a relatively recent technology that offers the solution for high-speed dicing for thin wafer. Main focus in this paper is established of ablation laser cut method for discrete devices and pre-production experiences. Others laser cut technologies are qualitatively discussed.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133357397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An experimental study on the application of Carbon nanotubes (CNTs) as thermal interfacial material in processor chip testing","authors":"Lee Yuan Thing, D. Mutharasu","doi":"10.1109/IEMT.2008.5507874","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507874","url":null,"abstract":"Increase in processor chip power has pushed the need for new thermal interface material (TIM) in test environment. TIM that provides high thermal conductivity and mechanical reliability in High volume manufacturing (HVM) is desired. This paper studies the Carbon nanotubes (CNTs) array as a feasible TIM solution in HVM test environment. Thermal resistance of CNTs array decorated silicon and bare silicon were obtained from experiment. CNTs array TIM shows 21.7% improvement in junction to case thermal resistance measurement under steady state force air convection experimental setup. Thermal resistance of CNT were then compare to Alloy thermal interface solution that has been deployed in HVM. Under the similar test setup, thermal resistance of CNTs array and Alloy TIM are measured as 0.296°C/Watt and 0.383°C/Watt respecitvely.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129267398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Keok, S. Too, J. Diep, Quah Hong Tat, A. Fumihiro, Kim Le
{"title":"Process development of fast-cure low stress lid adhesive for microprocessors","authors":"K. Keok, S. Too, J. Diep, Quah Hong Tat, A. Fumihiro, Kim Le","doi":"10.1109/IEMT.2008.5507786","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507786","url":null,"abstract":"A lid or heat spreader is used for packaging microprocessor chips. There are two primary functions for the lid: dissipate heat efficiently from the microprocessor and provide physical protection to the fragile silicon chip. To achieve these functions, lid material, thermal interface material and adhesive material, and assembly process are key areas that require development. Lid adhesive has a critical role in ensuring the whole microprocessor package meets thermal and thermomechanical reliability requirements. Lid adhesive has to provide good and consistent bonding strength between the lid and the substrate under various application conditions. At the same time, it also needs to absorb the stresses in the microprocessor package due to thermal mismatch between various materials: silicon, underfill, organic substrate, and lid. Another less known function of lid and adhesive is package warpage reduction. This paper discusses a low-stress lid adhesive material development that features a wide material processing window and fast-cure capability to improve assembly process throughput. Key material characteristics, including bonding strength, fracture mode, package warpage and reliability performance data will be presented to demonstrate the capability of the material to meet performance and reliability requirements for microprocessor packages.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122987992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation of novel reflow profile of no-clean fluxes to enhance flux stability and oxide layer removal of the high lead solder bump","authors":"N. Amin, A. Y. Cheah, Lam Zi Yi, Z. Kornain","doi":"10.1109/IEMT.2008.5507833","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507833","url":null,"abstract":"Various reflow profiles have been applied on different no-clean fluxes amount in removing the oxide layer of high lead solder bump. The wafers exposed to open air induce an oxide layer on the high lead solder bump. This oxide layer eventually creates the non wet phenomena in flip chip packaging. An experimental study is carried out by varying different soak time of the reflow profile to optimize the effectiveness of the flux in solving the eutectic and controlled collapse chip connection (C4) high lead bump issue, which indirectly solves the non wet issue. Visual inspection on high lead solder bump under high power microscope is carried out after reflow process. Die pull test is carried out on the solder joint strength analysis to test the solder bump strength. Besides, experiments on substrate cleanliness test, nonwet phenomena and die misalignment are also conducted with useful hints to be implemented.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124949721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Breakthrough of laser deflash system to improve productivity","authors":"Deng Bin, Shao Peng, Wang Yue","doi":"10.1109/IEMT.2008.5507858","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507858","url":null,"abstract":"This paper describes a new build-in-vision (BIV) and vertical laser cutting method to improve capacity of laser deflash system with maintaining 3 mils lead flash remains in miniature package such as SOD923. This equipment is developed by Leshan-Phoenix Semiconductor Co. Ltd. (LPS) and supplier. The traditional laser deflash system is equipped with pre-vision for package positioning, post-vision for lead frame positioning and laser cutting per transferred data from vision system. In order to avoid more than 3 mils tiny lead mold flash which was induced by blocking or shading laser beam couple with units that locating at far end from laser center focus point. Therefore, lead frame was subjected to “Three Indexes” using slantwise cutting concept. However, it takes longer cycle time and becomes bottleneck. The new laser deflash system is equipped with new designed build-in-vision and special telecentric laser beam focus system. Build-in-vision is consists of vision camera, lighting and special designed coupling mirror which is capable of penetrating through both vision lighting and laser beam. This design assures vision positioning inspection and laser cutting simultaneously. A special tele-centric lens was designed to change the angle of laser beam for controlling the reflection of laser beam away from focus-centre point. This is to ensure laser beam vertically in the whole laser cutting field. The new system has the capability with build-in-vision and vertical laser cutting design shows significant improvement on mechanical transfer time and laser cutting time.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128469524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Building a Delamination-free Electronic Package Using Thermal Analysis Data","authors":"S. Dal","doi":"10.1109/IEMT.2008.5507861","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507861","url":null,"abstract":"Package delamination is a product of chemical, mechanical and thermal incompatibilities. Thermal analysis methods are used to study these factors along with other techniques. One thermomechanical analysis (TMA) data that can be maximized in order to get a delamination-free combination of materials is the glass transition temperature (Tg) measurement. The thermograph produced contains information on Tg, coefficient of thermal expansion (CTE) and total expansion (dimension change). The technique shown in this paper is to combine different Tg thermographs of adhesives, encapsulants and metal parts in order to create a “package”. To keep the unit from “delaminating”, the thermographs have to be as uniform as possible when overlayed. At the very least, the graphs should be able to show which interfaces are at risk of delamination during certain assembly processes. The same concept is used if one intends to improve an existing process condition. Thermographs of copper leadframe (Cu LF), die attach (DA) adhesive and epoxy mold compound (EMC) samples are generated using cure profiles (for the polymers only) and a standard heating rate of 10°C/min. The resulting thermographs are overlayed and the best combination is chosen by visual comparison. The beauty of the technique is that it is simple, rich in technical basis and individual results can be easily stored in a database.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127021213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}