2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)最新文献_第2页

A novel push-pull sampling methodology for test production in semiconductor manufacturing industries 一种用于半导体制造行业测试生产的新型推挽抽样方法

2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT) Pub Date : 2008-11-01 DOI: 10.1109/IEMT.2008.5507804

Chow Leng Kwang, Ong Eu Chin

{"title":"A novel push-pull sampling methodology for test production in semiconductor manufacturing industries","authors":"Chow Leng Kwang, Ong Eu Chin","doi":"10.1109/IEMT.2008.5507804","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507804","url":null,"abstract":"This paper describes the use of a push-pull sampling methodology on test products to improve manufacturing efficiency. The conventional test technologies heavily rely on manufacturing operators to manually input the necessary information to a station controller for processing a test lot. This approach has resulted in some quality issues of sampling miscalculation owing to under-sample requirements in test processes. A robust solution is developed by applying a two-stage push-pull methodology in a new automated sampling system. The push-pull approach of automated sampling controls and propagates the correct sampling data to the operators for them to run test lots with the correct samples. The system has contributed to improving manufacturing capacity, creating robust controllable system, reducing human handling or dependency, and shortening the lead time to end customers. All these have resulted in effective manufacturing control to eliminate non-value added activities and zero repeated quality cases in the manufacturing test environment. The overall ROI (return of investment) realized by this system is a cost saving of million dollars, by mitigating the cost of human errors against reduction of production cost per unit.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124312862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A novel CMOS-compatible fabrication method for development of an electrostatically actuated micropump 一种用于开发静电驱动微泵的新型cmos兼容制造方法

2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT) Pub Date : 2008-11-01 DOI: 10.1109/IEMT.2008.5507836

Hing Wah Lee, M. R. Buyong, M. I. Syono, I. Azid

引用次数: 1

Nondestructive method of TIM bondline measurement in Flip Chips package 倒装芯片封装中TIM键合线的无损测量方法

2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT) Pub Date : 2008-11-01 DOI: 10.1109/IEMT.2008.5507830

H. Heng, V. Ben, K. Keok, Riemer Jay

{"title":"Nondestructive method of TIM bondline measurement in Flip Chips package","authors":"H. Heng, V. Ben, K. Keok, Riemer Jay","doi":"10.1109/IEMT.2008.5507830","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507830","url":null,"abstract":"This paper describes the method of using Acoustic Micro Imaging (AMI) technique as nondestructive method to measure the bond line thickness (BLT) of the thermal interface material (TIM) in Flip Chips package; this is an alternative to destructive physical analysis. The purpose of this study is to demonstrate the capability of AMI used to measure the BLT of TIM. The two interfaces of interest are Lid-to-TIM. and TIM-to-Silicon chip. AMI is a nondestructive inspection technique that utilizes high frequency ultrasound in the range of 5 to 500 MHz to: -determine interface bonding/adhesion detect -defects -characterize & measure material properties Acoustic Micro Imaging instrument shown here is an effective technique for nondestructively evaluating the TIM thickness. The images in this report demonstrate a few of many imaging and analysis techniques within AMI technology that are useful for production screening and in laboratory. These capabilities make it an excellent choice for a fast, reliable and accurate to measure the thermal interface material after joining the lid with the backside of the flip chip without manual cross section.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"2 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116861985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Crosstalk and switching noise mechanism study in high density wire-bond FPGA device 高密度线键FPGA器件串扰与开关噪声机理研究

2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT) Pub Date : 2008-11-01 DOI: 10.1109/EPTC.2008.4763415

S. Tan, Yee Huan Yew, Hong Shi

引用次数: 1

Chip-free singulation for medical application 用于医疗应用的无芯片模拟

2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT) Pub Date : 2008-11-01 DOI: 10.1109/IEMT.2008.5507867

A. Teng

{"title":"Chip-free singulation for medical application","authors":"A. Teng","doi":"10.1109/IEMT.2008.5507867","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507867","url":null,"abstract":"Singulation is one of the most damaging process steps in IC assembly because of the torque and force applied by the saw blade to abrade away silicon material on all 4 sides of the IC die. The removed material around the die creates a gap which allows the die to be freed from the wafer. If the abrasive singulation process is not controlled, the freed die may exhibit low mechanical strength due to chipping damage. This is particularly a problem because newer medical devices are designed with dimensions that are long and narrow in order to fit into small implantable or insertable products. Compared to the more square shaped IC dies, chipping is more of a problem on high aspect ratio dies because of the its susceptibility to resonance and vibration during blade dicing on the longer sides. For this paper, conventional dicing and Dice Before Grind (DBG) are compared. Mechanical test dies prepared from blank silicon wafers cut to >3.5 mm long 0.5 mm wide and 0.150 mm thick are prepared. High aspect ratios of 10:1 with various backside finishes will be compared for dicing quality and mechanical integrity. Using the proper grind wheels with the finer grit size, 100% yield for singulation resulting in higher strength devices can be obtained with good efficiency with dice before grind method.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127360751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Warpage measurements of laminate based BGA packages at elevated temperatures and comparison with real board assembly behaviour 基于层压板的BGA封装在高温下的翘曲测量和与实际电路板组装行为的比较

2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT) Pub Date : 2008-11-01 DOI: 10.1109/IEMT.2008.5507824

C. Birzer, M. Graml, M. Dittes, W. Mack

{"title":"Warpage measurements of laminate based BGA packages at elevated temperatures and comparison with real board assembly behaviour","authors":"C. Birzer, M. Graml, M. Dittes, W. Mack","doi":"10.1109/IEMT.2008.5507824","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507824","url":null,"abstract":"This paper is about warpage of laminate substrate based BGAs and fine pitch BGAs at lead-free board assembly reflow temperatures using shadow moiré technique. Various constructions (e.g. single die devices and multi chip modules) and different die and package sizes as well as different molding compound materials were considered in this study. A simple model for predicting high temperature warpage for single die devices based on the distance between package corner and die corner was developed. The comparison of the warpage results with and without moisture soaking according JEDEC MSL 3 did not exhibit a significant influence on high temperature warpage. The shadow moiré test results at elevated temperatures are compared with solder joint height distributions measured in cross sections after real lead-free board assembly. A clear correlation of the solder joint height distributions with the package warpage status at 170°C during cooling phase was found. This is much lower than the mominal solidification temperature of lead-free solder. This study helps to understand the influencing factors of BGA warpage and its role for board assembly.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130174688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Prediction studies on percolation threshold behaviour of silver filled epoxy composite for electrically conductive adhesives applications 导电胶粘剂用银填充环氧复合材料渗透阈值行为的预测研究

2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT) Pub Date : 2008-11-01 DOI: 10.1109/IEMT.2008.5507799

M. Zulkarnain, M. Mariatti, I. Azid

引用次数: 1

Effects of non-uniform base heating in multi stack microchannel heat sinks used for cooling high heat flux electronic chips and devices 用于冷却高热流密度电子芯片和器件的多堆微通道散热器中不均匀基底加热的影响

2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT) Pub Date : 2008-11-01 DOI: 10.1109/IEMT.2008.5507856

P. Hegde, K. N. Seetharamu

引用次数: 3

Application Of Ultra Low Loop gold wire bonding technique in Super Thin (Jedec Package Profile Height Sub Code “X2”) Quad Flat No Lead Package (QFN) 超低环金线键合技术在超薄(Jedec封装外形高度子码“X2”)四平无引线封装(QFN)中的应用

2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT) Pub Date : 2008-11-01 DOI: 10.1109/IEMT.2008.5507845

Tan Boo Wei, Wang Lei, K. Niu, Lu Hai Long

{"title":"Application Of Ultra Low Loop gold wire bonding technique in Super Thin (Jedec Package Profile Height Sub Code “X2”) Quad Flat No Lead Package (QFN)","authors":"Tan Boo Wei, Wang Lei, K. Niu, Lu Hai Long","doi":"10.1109/IEMT.2008.5507845","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507845","url":null,"abstract":"Quad Flat No Lead Package (QFN) with “Super Thin” package height of 0.3 to 0.4 mm (package profile height sub code “X2” per Jedec Standard) is designed with limited vertical space for wire loop height. Typical package construction consists of leadframe thickness, chip and chip attach adhesive thickness, mold (encapsulation) thickness left only 75 to 100 um (3 to 4 mils) space between chip surface and package surface which is available for wire bonding . Therefore wire bonding loop height in QFN-X2 package are typically controlled within less than 100um (4mils) as measured from chip surface to highest point of wire loop . Typically there are 3 areas to consider when developing gold wire bond techniques to achieve low loop height: 1. Stress level at the heat affected zone near wire exit above ball (1st bonds). 2. Consistency of wire loop height across all wires within same package. 3. Resistance to mold flow sweeping during molding (encapsulation process). There are two common wire bond techniques available to achieve wire loop height less than 100um (4mils) - bond stitch on ball (BSOB) and ultra low loop (ULL) forward bonding. This paper discusses the comparative performance and limitations of both wire bond techniques .","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122640642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Warpage simulation for chip-in-substrates 芯片基板翘曲模拟

2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT) Pub Date : 2008-11-01 DOI: 10.1109/IEMT.2008.5507803

J. Kim, Jupyo Hong, Shan Gao, Seogmoon Choi, S. Yi

引用次数: 0