Warpage simulation for chip-in-substrates

Abstract

In order to predict warpage of chip-in-substrate package, finite element analysis was carried out with modeling layers in chip and substrate and effective thermoelastic properties. The effects of design parameters such as pattern on the gap between chip and cavity, number of circuit layers, thickness and face direction of the chip, and gap width were investigated. The result shows that the warpage much depends on the internal structure and the effective thermoelastic properties.