Application Of Ultra Low Loop gold wire bonding technique in Super Thin (Jedec Package Profile Height Sub Code “X2”) Quad Flat No Lead Package (QFN)

Tan Boo Wei, Wang Lei, K. Niu, Lu Hai Long
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引用次数: 1

Abstract

Quad Flat No Lead Package (QFN) with “Super Thin” package height of 0.3 to 0.4 mm (package profile height sub code “X2” per Jedec Standard) is designed with limited vertical space for wire loop height. Typical package construction consists of leadframe thickness, chip and chip attach adhesive thickness, mold (encapsulation) thickness left only 75 to 100 um (3 to 4 mils) space between chip surface and package surface which is available for wire bonding . Therefore wire bonding loop height in QFN-X2 package are typically controlled within less than 100um (4mils) as measured from chip surface to highest point of wire loop . Typically there are 3 areas to consider when developing gold wire bond techniques to achieve low loop height: 1. Stress level at the heat affected zone near wire exit above ball (1st bonds). 2. Consistency of wire loop height across all wires within same package. 3. Resistance to mold flow sweeping during molding (encapsulation process). There are two common wire bond techniques available to achieve wire loop height less than 100um (4mils) - bond stitch on ball (BSOB) and ultra low loop (ULL) forward bonding. This paper discusses the comparative performance and limitations of both wire bond techniques .
超低环金线键合技术在超薄(Jedec封装外形高度子码“X2”)四平无引线封装(QFN)中的应用
Quad Flat No Lead封装(QFN)具有0.3至0.4 mm的“超薄”封装高度(封装轮廓高度子代码“X2”per Jedec标准),设计具有有限的垂直空间,用于线圈高度。典型的封装结构包括引线框架厚度,芯片和芯片附着的粘合剂厚度,模具(封装)厚度仅在芯片表面和封装表面之间留下75至100 um(3至4 mils)的空间,可用于导线粘合。因此,从芯片表面到线环最高点,QFN-X2封装中的线键合环高度通常控制在小于100um (4mils)的范围内。通常,在开发金丝键合技术以实现低环高度时,需要考虑3个方面:靠近钢丝出口的热影响区(第一键)的应力水平。2. 同一包装内所有电线的线圈高度一致。3.在成型(封装过程)中抗模流扫。有两种常见的金属丝粘合技术可用于实现金属丝环高度小于100um (4mils) -球上粘合(BSOB)和超低环(ULL)正向粘合。本文讨论了两种线键合技术的比较性能和局限性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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